OMAP3530, OMAP3525
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SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
OMAP3530 and OMAP3525 Applications Processors
Check for Samples: OMAP3530, OMAP3525
1 OMAP3530 and OMAP3525 Applications Processors
1.1
Features
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• OMAP3530 and OMAP3525 Devices:
– OMAP™ 3 Architecture
– MPU Subsystem
• Up to 720-MHz ARM® Cortex™-A8 Core
• NEON™ SIMD Coprocessor
– High-Performance Image, Video, Audio
(IVA2.2™) Accelerator Subsystem
• Up to 520-MHz TMS320C64x+™ DSP Core
• Enhanced Direct Memory Access (EDMA)
Controller (128 Independent Channels)
• Video Hardware Accelerators
– PowerVR® SGX™ Graphics Accelerator
(OMAP3530 Device Only)
• Tile-Based Architecture Delivering up to
10 MPoly/sec
• Universal Scalable Shader Engine: Multithreaded Engine Incorporating Pixel and
Vertex Shader Functionality
• Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0
• Fine-Grained Task Switching, Load
Balancing, and Power Management
• Programmable High-Quality Image AntiAliasing
– Fully Software-Compatible with C64x and
ARM9™
– Commercial and Extended Temperature
Grades
• Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+ DSP Core
– Eight Highly Independent Functional Units
• Six ALUs (32- and 40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture with Nonaligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+ Enhancements
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•
•
•
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Operation
C64x+ L1 and L2 Memory Architecture
– 32KB of L1P Program RAM and Cache
(Direct Mapped)
– 80KB of L1D Data RAM and Cache (2-Way
Set-Associative)
– 64KB of L2 Unified Mapped RAM and Cache
(4-Way Set-Associative)
– 32KB of L2 Shared SRAM and 16KB of L2
ROM
C64x+ Instruction Set Features
– Byte-Addressable (8-, 16-, 32-, and 64-Bit
Data)
– 8-Bit Overflow Protection
– Bit Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Additional Instructions to Support Complex
Multiplies
ARM Cortex-A8 Core
– ARMv7 Architecture
• TrustZone®
• Thumb®-2
• MMU Enhancements
– In-Order, Dual-Issue, Superscalar
Microprocessor Core
– NEON Multimedia Architecture
– Over 2x Performance of ARMv6 SIMD
– Supports Both Integer and Floating-Point
SIMD
– Jazelle® RCT Execution Environment
Architecture
– Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
– Embedded Trace Macrocell (ETM) Support
for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
– 16-KB Instruction Cache (4-Way Set-
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