SN74AVC16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES156G – DECEMBER 1998 – REVISED MAY 2005
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FEATURES
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Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA
at 2.5-V VCC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin Shrink
Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
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DESCRIPTION
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
- Output Voltage - V
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
V - Output Voltage - V
OL
2.8
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL - Output Current - mA
136
153
170
VCC = 2.5 V
VCC = 1.8 V
-160 -144 -128 -112 -96 -80 -64 -48
IOH - Output Current - mA
-32
-16
0
Figure 1. Output Voltage vs Output Current
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at
the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can
be retained or new data can be entered while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2005, Texas Instruments Incorporated
