MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P−channel and N−channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog−to−Digital and Digital−to−Analog conversions,
and (3) Magnitude and sign generation.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge−Clocked Design — Count Occurs on Positive Going
Edge of Clock
Single Pin Reset
Asynchronous Preset Enable Operation
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky Load Over the Rated Temperature Range
These Devices are Pb−Free and are RoHS Compliant
MC14516BCP
AWLYYWWG
1
1
SOIC−16
D SUFFIX
CASE 751B
Features
•
•
•
•
16
1
SOEIAJ−16
F SUFFIX
CASE 966
1
A
WL, L
YY, Y
WW, W
G
16
14516BG
AWLYWW
1
16
MC14516B
ALYWG
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Value
Unit
ORDERING INFORMATION
VDD
−0.5 to +18.0
V
Vin, Vout
−0.5 to VDD
+ 0.5
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
± 10
mA
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature (8−Second Soldering)
TL
260
°C
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 8
1
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused
outputs must be left open.
Publication Order Number:
MC14516B/D
