CS5521/22/23/24/28
16-Bit or 24-Bit, 2/4/8-Channel ADCs with PGIA
Features
General Description
l Low
The CS5521/22/23/24/28 are highly integrated ∆Σ Analog-to-Digital Converters (ADCs) which use chargebalance techniques to achieve 16-bit (CS5521/23) and
24-bit (CS5522/24/28) performance. The ADCs come as
either
two-channel
(CS5521/22),
four-channel
(CS5523/24), or eight-channel (CS5528) devices, and
include a low input current, chopper-stabilized instrumentation amplifier. To permit selectable input spans of
25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs
include a PGA (programmable gain amplifier). To accommodate ground-based thermocouple applications,
the devices include a Charge Pump Drive which provides a negative bias voltage to the on-chip amplifiers.
Input Current (100 pA), Chopper
Stabilized Instrumentation Amplifier
l Scalable Input Span (Bipolar/Unipolar)
- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V, 2.5 V,
5V
- External: 10 V, 100 V
l Wide
VREF Input Range (+1 to +5 V)
Order Delta-Sigma A/D Converter
l Easy to Use Three-wire Serial Interface Port
l Fourth
- Programmable/Auto Channel Sequencer with
Conversion Data FIFO
- Accessible Calibration Registers per Channel
- Compatible with SPITM and MicrowireTM
l System
and Self-Calibration
l Eight Selectable Word Rates
- Up to 617 Hz (XIN = 200 kHz)
- Single Conversion Settling
- 50/60 Hz ±3 Hz Simultaneous Rejection
l Single
+5 V Power Supply Operation
- Charge Pump Drive for Negative Supply
- +3 to +5 V Digital Supply Operation
l Low
Power Consumption: 5.5 mW
VA+
AGND
These devices also include a fourth order ∆Σ modulator
followed by a digital filter which provides eight selectable
output word rates. The digital filters are designed to settle
to full accuracy within one conversion cycle and when
operated at word rates below 30 Hz, they reject both 50
and 60 Hz interference.
These single supply products are ideal solutions for
measuring isolated and non-isolated, low-level signals in
process control applications.
ORDERING INFORMATION
See page 51.
VREF+ VREF-
DGND
X1
AIN1-
+
X20
AIN2+
AIN2AIN3+
Data
FIFO
X1
AIN1+
MUX
CS5524
Shown
Programmable
Gain
Differential
4th Order
Digital Filter
Calibration
Register
∆Σ
Modulator
X1
VD+
SCLK
Control
Register
AIN3AIN4+
AIN4Latch
Calibration
Memory
Calibration µC
CS
Clock
Gen.
Output
Register
SDI
SDO
NBV
CPD
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
A0 A1
XIN XOUT
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
MAY ‘00
DS317F2
1
CS5521/22/23/24/28
3.
4.
5.
6.
DS317F2
2.2.8.4 Charge Pump Disable ......................................................................... 29
2.2.8.5 Reset System Control Bits .................................................................. 29
2.2.8.6 Data Conversion Error Flags .............................................................. 29
2.3 Calibration ....................................................................................................................... 31
2.3.1 Self Calibration .................................................................................................... 31
2.3.2 System Calibration .............................................................................................. 32
2.3.3 Calibration Tips ................................................................................................... 34
2.3.4 Limitations in Calibration Range ......................................................................... 34
2.4 Performing Conversions and Reading the Data Conversion FIFO .................................. 34
2.4.1 Conversion Protocol ............................................................................................ 35
2.4.1.1 Single, One-Setup Conversion ........................................................... 35
2.4.1.2 Repeated One-Setup Conversions without Wait ................................ 35
2.4.1.3 Repeated One-Setup Conversions with Wait ..................................... 36
2.4.1.4 Single, Multiple-Setup Conversions .................................................... 36
2.4.1.5 Repeated Multiple-Setup Conversions without Wait ........................... 37
2.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................ 37
2.4.2 Calibration Protocol ............................................................................................. 38
2.4.3 Example of Using the CSRs to Perform Conversions and Calibrations .............. 38
2.5 Conversion Output Coding .............................................................................................. 40
2.5.1 Conversion Data FIFO Descriptions ................................................................... 41
2.6 Digital Filter ..................................................................................................................... 42
2.7 Clock Generator .............................................................................................................. 42
2.8 Power Supply Arrangements ........................................................................................... 43
2.8.1 Charge Pump Drive Circuits ............................................................................... 45
2.9 Digital Gain Scaling ........................................................................................................ 45
2.10 Getting Started .............................................................................................................. 46
2.11 PCB Layout ................................................................................................................... 47
PIN DESCRIPTIONS .............................................................................................................. 48
3.1 Clock Generator .............................................................................................................. 49
3.2 Control Pins and Serial Data I/O ..................................................................................... 49
3.3 Measurement and Reference Inputs ............................................................................... 49
3.4 Power Supply Connections ............................................................................................. 50
SPECIFICATION DEFINITIONS ............................................................................................. 51
ORDERING GUIDE ................................................................................................................ 51
PACKAGE DIMENSION DRAWINGS ................................................................................... 52
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