SN74AVCB164245
16-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES394D – JUNE 2002 – REVISED JUNE 2005
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FEATURES
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Member of the Texas Instruments Widebus™
Family
DOC™ Circuitry Dynamically Changes Output
Impedance, Resulting in Noise Reduction
Without Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA
at 2.5-V VCC
Control Inputs VIH/VIL Levels Are Referenced
to VCCB Voltage
If Either VCC Input Is at GND, Both Ports Are in
the High-Impedance State
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Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over Full 1.4-V to 3.6-V
Power-Supply Range
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The
A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage
bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.
To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND,
both ports are in the high-impedance state.
ORDERING INFORMATION
PACKAGE (1)
TA
ORDERABLE PART NUMBER
FBGA – GRD
74AVCB164245ZRDR
TSSOP – DGG
Tape and reel
SN74AVCB164245GR
TVSOP – DGV
Tape and reel
SN74AVCB164245VR
Tape and reel
SN74AVCB164245KR
VFBGA – ZQL (Pb-Free)
(1)
74AVCB164245GRDR
Tape and reel
VFBGA – GQL
–40°C to 85°C
Tape and reel
FBGA – ZRD (Pb-Free)
Tape and reel
74AVCB164245ZQLR
TOP-SIDE MARKING
WB4245
AVCB164245
WB4245
WB4245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
SN74AVCB164245
16-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES394D – JUNE 2002 – REVISED JUNE 2005
TERMINAL ASSIGNMENTS
(56-Ball GQL/ZQL Package) (1)
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
VCCB
VCCA
1A3
1A4
D
1B6
1B5
GND
GND
1A5
1A6
E
A
B
C
D
E
F
G
H
J
K
1B8
1B7
1A7
1A8
F
2B2
2A2
2A1
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
VCCB
VCCA
2A6
2A5
J
2B7
2B8
GND
GND
2A8
2A7
K
(1)
2B1
G
2DIR
NC
NC
NC
NC
2OE
NC - No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
TERMINAL ASSIGNMENTS
(54-Ball GRD/ZRD Package) (1)
1
B
3
4
5
6
1B1
NC
1DIR
1OE
NC
1A1
B
A
2
A
1B3
1B2
NC
NC
1A2
1A3
C
1B5
1B4
VCCB
VCCA
1A4
1A5
C
D
1B7
1B6
GND
GND
1A6
1A7
D
E
2B1
1B8
GND
GND
1A8
2A1
F
H
(1)
GND
GND
2A2
2A3
2B4
VCCB
VCCA
2A4
2A5
2B7
2B6
NC
NC
2A6
2A7
J
G
2B2
2B5
H
F
2B3
G
E
2B8
NC
2DIR
2OE
NC
2A8
NC - No internal connection
xxxxx
J
xxxxx
xxxxx
xxxxx
xxxxx
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
3
