MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4-Wide OR-AND/OR-AND
Gate
MC10121
The MC10121 is a basic logic building block providing the simultaneous
OR–AND/OR–AND–Invert function, useful in data control and digital multiplexing
applications.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
PD = 100 mW typ/pkg (No Load)
tpd = 2.3 ns typ
tr, tf = 2.5 ns typ (20%–80%)
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
4
5
DIP
PIN ASSIGNMENT
6
7
9
VCC1
1
16
VCC2
AOUT
2
3
10
2
15
A4IN
11
AOUT
3
14
A4IN
12
13
A1IN
4
13
A4IN
14
A1IN
5
12
A3IN
15
A1IN
6
11
A3IN
A2IN
7
10
A2IN, A3IN
VEE
8
9
A2IN
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–73
REV 5