SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
D Member of the Texas Instruments
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
description
This 12-bit to 24-bit multiplexed D-type latch is
designed for 1.65-V to 3.6-VCC operation.
The SN74ALVCH16260 is used in applications in
which two separate data paths must be
multiplexed onto, or demultiplexed from, a single
data path. Typical applications include
multiplexing and/or demultiplexing address and
data
information
in
microprocessor
or
bus-interface applications. This device also is
useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and
2B1–2B12) are available for address and/or data
transfer. The output-enable (OE1B, OE2B, and
OEA) inputs control the bus transceiver functions.
The OE1B and OE2B control signals also allow
bank control in the A-to-B direction.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B,
LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the
latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16260 is characterized for operation from –40°C to 85°C.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–35
SN74ALVCH16260
12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES046E – JULY 1995 – REVISED FEBRUARY 1999
logic diagram (positive logic)
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
2
27
30
55
56
29
1
28
G1
A1
C1
1
1D
8
23
1B1
1
C1
1D
6
2B1
C1
1D
C1
1D
To 11 Other Channels
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3–37