SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181E – DECEMBER 1982 – REVISED AUGUST 2003
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 20-µA Max ICC
SN54HC00 . . . J OR W PACKAGE
SN74HC00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Typical tpd = 8 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
1B
1A
NC
VCC
4B
SN54HC00 . . . FK PACKAGE
(TOP VIEW)
VCC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
NC
4Y
NC
3B
2Y
GND
NC
3Y
3A
1A
1B
1Y
2A
2B
2Y
GND
D
D
D
NC – No internal connection
description/ordering information
The ’HC00 devices contain four independent 2-input NAND gates. They perform the Boolean function
Y = A • B or Y = A + B in positive logic.
ORDERING INFORMATION
PACKAGE†
TA
PDIP – N
ORDERABLE
PART NUMBER
Tube of 25
Tube of 50
SN74HC00D
Reel of 2500
SOIC – D
SN74HC00N
SN74HC00DR
TOP-SIDE
MARKING
SN74HC00N
HC00
Reel of 250
SN74HC00DT
SOP – NS
Reel of 2000
SN74HC00NSR
HC00
SSOP – DB
Reel of 2000
SN74HC00DBR
HC00
Tube of 90
SN74HC00PW
Reel of 2000
SN74HC00PWR
Reel of 250
SN74HC00PWT
CDIP – J
Tube of 25
SNJ54HC00J
SNJ54HC00J
CFP – W
Tube of 150
SNJ54HC00W
SNJ54HC00W
LCCC – FK
–40°C 85°C
–40 C to 85 C
Tube of 55
SNJ54HC00FK
TSSOP – PW
–55°C 125°C
–55 C to 125 C
HC00
SNJ54HC00FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54HC00, SN74HC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCLS181E – DECEMBER 1982 – REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC00
SN74HC00
MIN
MIN
MAX
2V
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
1.9
1.998
1.9
4.4
4.499
4.4
4.4
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
UNIT
1.9
4.5 V
6V
IOH = –20 µA
A
MAX
V
5.34
2V
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VI = VCC or 0
VI = VCC or 0,
IO = 0
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
VI = VIH or VIL
0.1
6V
IOL = 20 µA
A
VOL
0.002
±0.1
±100
±1000
±1000
nA
2
40
20
µA
3
10
10
10
pF
6V
Ci
2 V to 6 V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC00
SN74HC00
MIN
MIN
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
45
90
135
115
tpd
A or B
Y
4.5 V
9
18
27
23
6V
8
15
23
20
MIN
MAX
MAX
2V
Y
38
75
110
8
15
22
19
6
13
19
ns
95
4.5 V
6V
tt
UNIT
16
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
POST OFFICE BOX 655303
No load
• DALLAS, TEXAS 75265
TYP
20
UNIT
pF
3
