PI2EQX5804
5.0Gbps 4-Lane PCI Express Gen2 Re-Driver
with Equalization & Emphasis
Features
Description
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Pericom Semiconductor’s PI2EQX5804 is a low power,
PCI-express compliant signal re-driver. The device provides
programmable equalization, amplification, and de-emphasis by
using 8 select bits, to optimize performance over a variety of
physical mediums by reducing Inter-symbol interference.
Up to 5.0Gbps PCI Express Gen-2 Serial Re-driver
Supporting 8 differential channels or 4 lanes of PCIe Interface
Pin strapped and I2C configuration controls (3.3V Tolerant)
Adjustable receiver equalization
Adjustable transmitter amplitude and de-emphasis
Variable input an output termination
1:2 channel broadcast
Channel loop-back
Electrical Idle fully supported
Receiver detect and individual output control
Single supply voltage, 1.2V ± 0.05V
Power down modes
Packaging: 100-contact LFBGA, Pb-free & Green
PI2EQX5804 supports eight 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI-express signal before the re-driver,
whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX5804 also provides power management Stand-by mode
operated by a Power Down pin.
Pin Configuration (Top-Side View)
Block Diagram
3
4
5
6
7
8
9
10
B0TX-
B0TX+
VDD
SCL
SDA
VDD
B0RX+
B0RX-
VDD
B A1RX+
GND
GND
A0RX -
DE_A
VDD
A0TX-
GND
GND
A1TX+
C A1RX-
GND
GND
A0RX+
RES_A# PD#
A0TX+
GND
GND
A1TX -
1
+
−
xyRx+
−
A
VDD
+
xyRx-
Output
Controls
Input level detect
to control logic
2
xyTx+
xyTx-
+
+
A
xyTx+
−
Equalizer
xyTx-
Equalizer
Output
Controls
B
Input level detect
to control logic
xyRx+
−
−
+
xyRx-
+
Sy_x
Dy_x
SDA
SCL
LB#
VDD
D2_A PRSNT2#
VDD
B1RX- B1RX+ VDD
D1_A
S0_A
RXD_A S1_A
SIG_A RX50_A
S1_B
RXD_B S0_B
A1
SEL2_B
LB#
SEL1_B SEL0_B
VDD
A2TX+
A2TX -
VDD
B3RX -
GND
GND
B2RX+
B3RX+
GND
GND B2RX-
RXD_x
RES_x
G
VDD
A2RX-
A2RX+
VDD
H
Power
Management
I2C Control
F RX50_B SIG_B
B2TX+
GND
GND
B3TX-
J B2TX-
GND
GND
B3TX+ RES_B# D1_B
MODE D0_B
DE_B
A0
Ax
K
07-0260
B1TX+ B1TX-
Mode
Control registers
& logic
DE_x
PD#
VDD
E SEL0_A SEL1_A SEL2_A D0_A
Data Lane Repeats 4 Times
SELy_x
D
−
1
VDD
A3RX+ A3RX-
VDD
D2_B
A4
VDD
A3TX-
PS8926A
A3TX+
VDD
11/19/07
