Revision 13
DS2136
40MX and 42MX FPGA Families
Features
HiRel Features
•
Commercial, Industrial, Automotive,
Temperature Plastic Packages
•
High Capacity
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
•
Single-Chip ASIC Alternative
•
3,000 to 54,000 System Gates
•
Up to 2.5 kbits Configurable Dual-Port SRAM
•
Fast Wide-Decode Circuitry
•
Ceramic Devices Available to DSCC SMD
•
Up to 202 User-Programmable I/O Pins
Military
QML Certification
•
and
Ease of Integration
High Performance
•
Mixed-Voltage Operation (5.0 V or 3.3 V for core and
I/Os), with PCI-Compliant I/Os
•
5.6 ns Clock-to-Out
•
250 MHz Performance
•
Up to 100% Resource Utilization and 100% Pin Locking
•
5 ns Dual-Port SRAM Access
•
Deterministic, User-Controllable Timing
•
100 MHz FIFOs
•
•
7.5 ns 35-Bit Address Decode
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
•
Low Power Consumption
•
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
10
Dedicated Flip-Flops
–
–
348
624
954
1,230
Maximum Flip-Flops
147
273
516
928
1,410
1,822
Clocks
1
1
2
2
2
6
User I/O (maximum)
57
69
104
140
176
202
PCI
–
–
–
–
Yes
Yes
Boundary Scan Test (BST)
–
–
–
–
Yes
Yes
44, 68
100
80
–
–
–
44, 68, 84
100
80
–
–
–
84
100, 144, 160
100
176
–
–
132
84
100, 160, 208
100
176
–
–
84
160, 208
–
176
–
–
–
208, 240
–
–
208, 256
272
Clock-to-Out
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
CPGA
August 2015
© 2015 Microsemi Corporation
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