2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
Data Sheet
FEATURES
GENERAL DESCRIPTION
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) at 3.6 V
Power-down to 120 nA at 3 V, 400 nA at 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Readback
Buffered/unbuffered reference inputs
20 ns WR time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
APPLICATIONS
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
The GAIN pin on these devices allows the output range to be
set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
VDD
AGND
VREFAB
DGND
VREFCD
POWER-ON
RESET
AD5348
BUF
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
VOUTD
WR
INPUT
REGISTER
DAC
REGISTER
STRING
DAC E
BUFFER
VOUTE
A2
INPUT
REGISTER
DAC
REGISTER
STRING
DAC F
BUFFER
VOUTF
A1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC G
BUFFER
VOUTG
INPUT
REGISTER
DAC
REGISTER
STRING
DAC H
BUFFER
VOUTH
GAIN
DB11
.
.
.
DB0
CS
RD
A0
INTERFACE
LOGIC
VOUTA
POWER-DOWN
LOGIC
LDAC
VREFGH
VREFEF
03331-0-001
CLR
PD
Figure 1.
1
Protected by U.S. Patent No. 5,969,657.
Rev. A
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