HIGH-SPEED 3.3V
32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features:
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True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 7.5ns (max.)
Low-power operation
– IDT70V9279/69S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9279/69L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
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IDT70V9279/69S/L
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
R/WR
UBL
UBR
CE0L
CE0R
1
0
0/1
1
0
CE1L
0/1
CE1R
LBL
OEL
LBR
OER
FT/PIPEL
0/1
1b 0bb
a 1a 0a
0a 1a
a
0b 1b
b
0/1
FT/PIPER
,
I/O8L-I/O15L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0L-I/O7L
I/O0R-I/O7R
A14R(1)
A14L(1)
A0L
CLKL
ADSL
CNTEN L
Counter/
Address
Reg.
MEMORY
ARRAY
CNTRSTL
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3743 drw 01
NOTE:
1. A14X is a NC for IDT70V9269.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC 3743/11
IDT70V9279/69S/L
High-Speed 32/16K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (3)
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A14L(1)
A0R - A14R(1)
Address
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
CLKL
CLKR
Clock
UBL
UBR
Upper Byte Select(2)
LBL
LBR
Lower Byte Select(2)
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through / Pipeline
VDD
Power (3.3V)
VSS
NOTES:
1. Address A14X is a NC for IDT70V9269.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CE0 and CE1 are single buffered when FT/PIPE = V IL,
CE0 and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
Ground (0V)
3743 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0(5)
CE 1(5)
UB(4)
LB(4)
R/W
Upper Byte
I/O8-15
Lower Byte
I/O0-7
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
H
L
L
High-Z
DATA IN
Write to Lower Byte Only
X
↑
L
H
L
L
L
DATA IN
DATA IN
Write to Both Bytes
L
↑
L
H
L
H
H
DATAOUT
High-Z
Read Upper Byte Only
L
↑
L
H
H
L
H
High-Z
DATAOUT
Read Lower Byte Only
L
↑
L
H
L
L
H
DATAOUT
DATAOUT
Read Both Bytes
H
↑
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
MODE
3743 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4 LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.42
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