74ABT574A
Octal D-type flip-flop; 3-state
Rev. 2 — 23 November 2012
Product data sheet
1. General description
The 74ABT574A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT574A is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The clock input (CP) and output enable input (OE) control gates, control the two
sections of the device independently. The state of each data input (Dn, one set-up time
before the Low-to-High clock transition) is transferred to the Q output of the corresponding
flip-flop.
When OE is Low, the stored data appears at the outputs. When OE is High, the outputs
are in the High-impedance “off” state, which means they do not drive or load the bus.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the clock operation.
2. Features and benefits
74ABT574A is flow-through pinout version of 74ABT374A
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State outputs for bus interfacing
Power-on 3-state
Power-on reset
Common output enable
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Live insertion/extraction permitted.
74ABT574A
NXP Semiconductors
Octal D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
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2(
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4
'
4
'
4
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4
'
4
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2(
9&&
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4
'
4
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4
'
4
'
4
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4
'
4
'
4
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4
'
4
*1'
&3
'
4
*1'
DDD
Fig 4.
&3
DDD
Pin configuration DIP20 and SO20
Fig 5.
Pin configuration SSOP20 and TSSOP20
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
OE
1
3-state output enable input (active LOW)
D0, D1, D2, D3, D4, D5, D6, D7
2, 3, 4, 5, 6, 7, 8, 9
data input
GND
10
ground (0 V)
CP
11
clock pulse input (active rising edge)
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
19, 18, 17, 16, 15, 14, 13, 12
3-state flip-flop output
VCC
20
supply voltage
74ABT574A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 23 November 2012
© NXP B.V. 2012. All rights reserved.
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