SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002
D Designed to Ensure Defined Voltage Levels
D
D
D
D
D
D
D
D
DW OR NS PACKAGE
(TOP VIEW)
on Floating Bus Lines in CMOS Systems
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Reduces Undershoot and Overshoot
Caused By Line Reflections
Repetitive Peak Forward
Current . . . IFRM = 100 mA
Inputs Are TTL-Voltage Compatible
Low Power Consumption (Like CMOS)
Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D1
D2
D3
D4
GND
GND
D5
D6
D7
D8
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
D16
D15
D14
D13
VCC
VCC
D12
D11
D10
D9
description/ordering information
This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp
the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device
also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path
between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or
pulldown resistors.
The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The
feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state
generated by an active driver before the bus switches to the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
Tube
−40°C to 85°C
40 C 85 C
SOP − NS
†
SN74ACT1073DW
Tape and reel
SN74ACT1073DWR
Tape and reel
SOIC − DW
SN74ACT1073NSR
TOP-SIDE
MARKING
ACT1073
ACT1073
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TA = 25°C
TEST CONDITIONS
MIN
TYP†
MAX
MIN
MAX
UNIT
IIL
VCC = 4.5 to 5.5 V,
VI = 0.8 V
0.15
0.3
0.9
0.1
1
mA
IIH
VCC = 4.5 to 5.5 V,
VI = 2.5 V
−0.2
−0.5
−1.4
−0.15
−1.5
mA
VIKL
IIN = −18 mA
V
VIKH
IIN = 18 mA
ICC‡
VCC = 5.5 V,
Inputs open
ΔICC§
One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
−1.5
−1.5
VCC+2
VCC+2
V
4
40
μA
0.9
1
mA
3
pF
†
All typical values are at VCC = 5 V.
Inputs may be set high or low prior to the ICC measurement.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V .
CC
‡
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
