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74F181D
54F 74F181 4-Bit Arithmetic Logic Unit General Description Features The ’F181 is a 4-bit Arithmetic logic Unit (ALU) which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations It is 40% faster than the Schottky ALU and only consumes 30% as much power Y Package Number Military 74F181PC N24A 24-Lead (0 600 Wide) Molded Dual-In-Line N24C 24-Lead (0 300 Wide) Molded Dual-In-Line 54F181DM (Note 2) J24A 24-Lead Ceramic Dual-In-Line 54F181SDM (Note 2) J24F 24-Lead (0 300 ) Ceramic Dual-In-Line M24B 24-Lead (0 300 ) Molded Small Outline JEDEC W24C 24-Lead Cerpack E28A 24-Lead Ceramic Leadless Chip Carrier Type C 74F181SC (Note 1) 54F181FM (Note 2) 54F181LM (Note 2) Note 1 Devices also available in 13 reel Use suffix e SCX et 74F181SPC Package Description e Commercial Y Full lookahead for high-speed arithmetic operation on long words Guaranteed 4000V minimum ESD protection bs ol Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams O Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9491 – 2 TL F 9491 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9491 RRD-B30M105 Printed in U S A 54F 74F181 4-Bit Arithmetic Logic Unit August 1995 ’F181 Operation Table S3 Logic (M e H) Arithmetic (M e L C0 e Inactive) Arithmetic (M e L C0 e Active) L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A AB AaB Logic ‘‘1’’ AaB B AZB AaB AB AZB B AaB Logic ‘‘0’’ AB AB A A minus 1 A B minus 1 A B minus 1 minus 1 (2s comp ) A plus (A a B) A B plus (A a B) A minus B minus 1 AaB A plus (A a B) A plus B A B plus (A a B) AaB A plus A (2 c A) A plus A B A plus A B A A AB AB Zero A plus (A a B) plus 1 A B plus (A a B) plus 1 A minus B A a B plus 1 A plus (A a B plus 1 A plus B plus 1 A B plus (A a B) plus 1 A a B plus 1 A plus A (2 c A) plus 1 A plus A B plus 1 A plus A B plus 1 A plus 1 L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A AaB AB Logic ‘‘0’’ AB B AZB AB AaB AZB B AB Logic ‘‘1’’ AaB AaB A A AaB AaB minus 1 (2s comp ) A plus (A B) A B plus (A a B) A minus B minus 1 A B minus 1 A plus A B A plus B A B plus (A a B) A B minus 1 A plus A (2 c A) A plus (A a B) A plus (A a B) A minus 1 A plus 1 A a B plus 1 A a B plus 1 Zero A plus A B plus 1 A B plus (A a B) plus 1 A minus B AB A plus A B plus 1 A plus B plus 1 A B plus (A a B) plus 1 AB A plus A (2 c A) plus 1 A plus (A a B) plus 1 A plus (A a B) plus 1 A bs ol b All Input Data True S2 et a All Input Data Inverted S1 e S0 O c A Input Data Inverted B Input Data True d A Input Data True B Input Date Inverted L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A AaB AB Logic ‘‘1’’ AB B AZB AaB AaB AZB B AaB Logic ‘‘0’’ AB AB A A minus 1 A B minus 1 A B minus 1 minus 1 (2s comp ) A plus (A a B) A B plus (A a B) A plus B AaB A plus (A a B) A minus B minus 1 A B plus (A a B) AaB A plus A (2 c A) A plus A B A plus A B A A AB AB Zero A plus (A a B) plus 1 A B plus (A a B) plus 1 A plus B plus 1 A a B plus 1 A plus (A a B) plus 1 A minus B A B plus (A a B) plus 1 A a B plus 1 A plus A (2 c A) plus 1 A plus A B plus 1 A plus A B plus 1 A plus 1 L H L H L H L H L H L H L H L H L L H H L L H H L L H H L L H H L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H A AB AaB Logic ‘‘0’’ AaB B AZB AB AB AZB B AB Logic ‘‘1’’ AaB AaB A A AaB AaB minus 1 (2s comp ) A plus A B A B plus (A a B) A plus B A B minus 1 A plus A B A minus B minus 1 A B plus (A a B) A B minus 1 A plus A (2 c A) A plus (A a B) A plus (A a B) A minus 1 A plus 1 A a B plus 1 A a B plus 1 Zero A plus A B plus 1 A B plus (A a B) plus 1 A plus B plus 1 AB A plus A B plus 1 A minus B A B plus (A a B) plus 1 AB A plus A (2 c A) plus 1 A plus (A a B) plus 1 A plus (A a B) plus 1 A 3
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