3D7424
MONOLITHIC QUAD 4-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7424)
FEATURES
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PACKAGES
Four indep’t programmable lines on a single chip
All-silicon CMOS technology
Low quiescent current (5mA typical)
Leading- and trailing-edge accuracy
Vapor phase, IR and wave solderable
Increment range: 0.75ns through 400ns
Delay tolerance: 3% or 2ns (see Table 1)
Line-to-line matching: 1% or 1ns typical
Temperature stability: ±1.5% typical (-40C to 85C)
Vdd stability: ±0.5% typical (4.75V to 5.25V)
Minimum input pulse width: 10% of total delay
I1
SC
I2
I3
I4
SI
GND
1
2
3
4
5
6
7
VDD
AL
O1
SO
O2
O3
O4
14
13
12
11
10
9
8
SOIC-14
3D7424D-xx
For mechanical dimensions, click here.
For package marking details, click here.
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7424 device is a small, versatile, quad 4-bit programmable
monolithic delay line. Delay values, programmed via the serial interface,
can be independently varied over 15 equal steps. The step size (in ns) is
determined by the device dash number. Each input is reproduced at the
corresponding output without inversion, shifted in time as per user
selection. For each line, the delay time is given by:
I1-I4
O1-O4
AL
SC
SI
SO
VDD
GND
TDn = T0 + An * TI
Signal Inputs
Signal Outputs
Address Latch In
Serial Clock In
Serial Data In
Serial Data Out
5.0V
Ground
where T0 is the inherent delay, An is the delay address of the n-th line
and TI is the delay increment (dash number). The desired addresses are
shifted into the device via the SC and SI inputs, and the addresses are latched using the AL input. The
serial interface can also be used to enable/disable each delay line. The 3D7424 operates at 5 volts and
has a typical T0 of 6ns. The 3D7424 is TTL/CMOS-compatible, capable of sourcing or sinking 4mA loads,
and features both rising- and falling-edge accuracy. The device is offered in a space saving surface mount
14-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DELAYS & TOLERANCES (NS)
Inherent
Total
Relative
Delay
Delay
Tolerance
Part
Number
Delay
Step
3D7424D-.75
3D7424D-1
3D7424D-1.5
3D7424D-2
3D7424D-4
3D7424D-5
3D7424D-10
3D7424D-15
3D7424D-20
3D7424D-40
3D7424D-50
3D7424D-100
3D7424D-200
3D7424D-400
.75 ± 0.19
1.0 ± 0.25
1.5 ± 0.38
2.0 ± 0.50
4.0 ± 1.00
5.0 ± 1.25
10 ± 2.50
15 ± 3.75
20 ± 5.00
40 ± 10.0
50 ± 10.0
100 ± 12.5
200 ± 20.0
400 ± 40.0
6.0 ± 2.0 17.25 ± 2.0 3% or 0.50ns
6.0 ± 2.0
21.0 ± 2.0 3% or 0.50ns
6.0 ± 2.0
28.5 ± 2.0 3% or 0.50ns
6.0 ± 2.0
36.0 ± 2.0 3% or 0.75ns
6.0 ± 2.0
66.0 ± 2.0 3% or 0.75ns
6.0 ± 2.0
81.0 ± 2.5 3% or 0.75ns
6.0 ± 2.0
156 ± 5.0 3% or 1.25ns
6.0 ± 2.0
231 ± 7.5 3% or 1.88ns
6.0 ± 2.0
306 ± 10 3% or 2.50ns
6.0 ± 2.0
606 ± 20 3% or 5.00ns
6.0 ± 2.0
756 ± 25 3% or 6.25ns
6.0 ± 2.0
1506 ± 50 3% or 12.5ns
6.0 ± 2.0 3006 ± 100 3% or 25.0ns
6.0 ± 2.0 6006 ± 200 3% or 50.0ns
INPUT RESTRICTIONS
Max Frequency
Min Pulse Width
Recom’d
19 MHz
16 MHz
12 MHz
9.2 MHz
5.0 MHz
4.1 MHz
2.1 MHz
1.4 MHz
1.0 MHz
550 KHz
440 KHz
220 KHz
110 KHz
55 KHz
Absolute
166 MHz
166 MHz
111 MHz
83 MHz
83 MHz
66 MHz
33 MHz
22 MHz
16 MHz
8.3 MHz
6.6 MHz
3.3 MHz
1.6 MHz
833 KHz
Recom’d
26 ns
32 ns
43 ns
54 ns
99 ns
122 ns
234 ns
347 ns
459 ns
909 ns
1.2 us
2.3 us
4.5 us
9.0 us
Absolute
3.0 ns
3.0 ns
4.5 ns
6.0 ns
6.0 ns
7.5 ns
15.0 ns
22.5 ns
30.0 ns
60.0 ns
75.0 ns
150 ns
300 ns
600 ns
NOTE: Any increment between 0.75ns and 400ns not shown is also available as standard
See page 4 for details regarding input restrictions
2007 Data Delay Devices
Doc #06019
6/25/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
3D7424
APPLICATION NOTES (CONT’D)
DELAY ACCURACY
DELAY STABILITY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the differential nonlinearity (DNL), also referred
to as the increment error. It is defined as the
deviation of the delay step at a given address
from its nominal value. For all dash numbers, the
DNL is within 1/4 LSB at every address (see
Table 1: Delay Step).
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D7424 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
With regard to stability, the delay of the 3D7424
at a given address, i, can be split into two
components: the inherent delay (T0) and the
relative delay (Ti – T0). These components exhibit
very different stability coefficients, both of which
must be considered in very critical applications.
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The thermal coefficient of the relative delay is
limited to ±250 PPM/C, which is equivalent to a
variation, over the -40C to 85C operating range,
of ±1.5% from the room-temperature delay
settings. This holds for dash numbers greater
than 1. For smaller dash numbers, the thermal
drift will be larger and will always be positive. The
thermal coefficient of the inherent delay is
nominally +15ps/C for all dash numbers.
The relative error is defined as follows:
erel = (Ti – T0) – i * Tinc
where i is the address, Ti is the measured delay
at the i’th address, T0 is the measured inherent
delay, and Tinc is the nominal increment. It is very
similar to the INL, but simpler to calculate. For
most dash numbers, the relative error is less than
1/8 LSB at every address (see Table 1: Relative
Tolerance).
The power supply sensitivity of the relative delay
is ±0.5% over the 4.75V to 5.25V operating
range, with respect to the delay settings at the
nominal 5.0V power supply. This holds for all
dash numbers greater than 1. For smaller dash
numbers, the voltage sensitivity will be greater
and will always be negative. The sensitivity of the
inherent delay is nominally -1ps/mV for all dash
numbers.
The absolute error is defined as follows:
eabs = Ti – (Tinh + i * Tinc)
where Tinh is the nominal inherent delay. The
absolute error tolerance is given for addresses 0
and 15 (see Table 1: Inherent Delay, Total Delay,
respectively). At any intermediate address, the
tolerance can be found via linear interpolation of
the address 0 & address 15 tolerances.
The matching error is a measure of how well the
delay of the four lines track each other when they
are all programmed to the same address. The
lines are typically matched to within 1% or 1ns,
whichever is greater, for all addresses and all
dash numbers.
3D7424
SI
FROM
WRITING
DEVICE
SO
SC
AL
3D7424
SI
SC
SO
3D7424
SI
AL
SC
SO
AL
TO
NEXT
DEVICE
Figure 3: Cascading Multiple Devices
Doc #06019
6/25/2007
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
