HOME＞在庫検索＞在庫情報
74F273NB
54F 74F273 Octal D Flip-Flop General Description Features The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements Y Commercial Package Number Military 74F273PC Y Y Y Y Y Y Y Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous Master Reset See ’F377 for clock enable version See ’F373 for transparent latch version See ’F374 for TRI-STATE version Guaranteed 4000V minimum ESD protection Package Description N20A 54F273DM (Note 2) 20-Lead (0 300 Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line 74F273SC (Note 1) M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC 74F273SJ (Note 1) M20D 20-Lead (0 300 Wide) Molded Small Outline EIAJ 54F273FM (Note 2) W20A 20-Lead Cerpack 54F273LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9511 – 3 TL F 9511 – 5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9511 RRD-B30M75 Printed in U S A 54F 74F273 Octal D Flip-Flop May 1995 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b 65 C to a 150 b 55 C to a 125 b 55 C to a 175 b 55 C to a 150 Ambient Temperature under Bias Junction Temperature under Bias Plastic Free Air Ambient Temperature Military Commercial C C C C b 55 C to a 125 C 0 C to a 70 C Supply Voltage Military Commercial a 4 5V to a 5 5V a 4 5V to a 5 5V VCC Pin Potential to Ground Pin b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) b 30 mA to a 5 0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (min) 4000V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs DC Electrical Characteristics Symbol 54F 74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Mil 10% VCC 5% VCC Output LOW Voltage Mil 10% VCC 5% VCC IIH Input HIGH Current IBVI Typ Units VCC Conditions Max 20 V Recognized as a HIGH Signal 08 V Recognized as a LOW Signal b1 2 V 25 25 27 Min IIN e b18 mA IOH e b1 mA V Min 05 05 05 V Min 54F 74F 20 0 50 mA Max VIN e 2 7V Input HIGH Current Breakdown Test 54F 74F 100 70 mA Max VIN e 7 0V ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 00 IID e 1 9 mA All other pins grounded IOD Output Leakage Circuit Current 74F 3 75 mA 00 VIOD e 150 mV All other pins grounded IIL Input LOW Current VOL IOS Output Short-Circuit Current ICCH ICCL 4 75 IOL e 20 mA b0 6 3 Max VIN e 0 5V mA Max VOUT e 0V 44 56 Power Supply Current mA b 150 b 60 mA Max CP e L Dn e MR e HIGH
見積依頼→在庫確認→見積回答→注文→検収→支払 となります。
