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74F373
54F 74F373 Octal Transparent Latch with TRI-STATE Outputs General Description Features The ’F373 consists of eight latches with TRI-STATE outputs for bus organized system applications The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH When LE is LOW the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state Y e Y Package Number Military 74F373PC Eight latches in a single package TRI-STATE outputs for bus interfacing Guaranteed 4000V minimum ESD protection Package Description N20A 54F373DM (QB) 20-Lead (0 300 Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line et Commercial Y 74F373SC (Note 1) M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC 74F373SJ (Note 1) M20D 20-Lead (0 300 Wide) Molded Small Outline EIAJ MSA20 20-Lead Molded Shrink Small Outline EIAJ Type II 54F373FM (QB) W20A 20-Lead Cerpack 54F373LM (QB) E20A 20-Lead Ceramic Leadless Chip Carrier Type C bs ol 74F373MSA (Note 1) Note 1 Devices also available in 13 reel Use suffix e SCX SJX and MSAX Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC SSOP and Flatpak O IEEE IEC TL F 9523–4 Pin Assignment for LCC TL F 9523 – 3 TL F 9523 – 2 TL F 9523–1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9523 RRD-B30M75 Printed in U S A 54F 74F373 Octal Transparent Latch with TRI-STATE Outputs May 1995 Absolute Maximum Ratings (Note 1) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0 5V to VCC Standard Output b 0 5V to a 5 5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b 65 C to a 150 C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55 C to a 125 C b 55 C to a 175 C b 55 C to a 150 C VCC Pin Potential to Ground Pin ESD Last Passing Voltage (Min) Recommended Operating Conditions b 0 5V to a 7 0V b 0 5V to a 7 0V Input Voltage (Note 2) Input Current (Note 2) 4000V Free Air Ambient Temperature Military Commercial b 30 mA to a 5 0 mA Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied b 55 C to a 125 C 0 C to a 70 C Supply Voltage Military Commercial Note 2 Either voltage limit or current limit is sufficient to protect inputs a 4 5V to a 5 5V a 4 5V to a 5 5V Symbol e DC Electrical Characteristics 54F 74F Parameter Typ Units VCC Conditions Max VIH Input HIGH Voltage 20 VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage et Min IIH IBVI ICEX VID 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC V V 25 24 25 24 27 27 V Recognized as a LOW Signal Min IIN e b18 mA Min IOH IOH IOH IOH IOH IOH e e e e e e b 1 mA b 3 mA b 1 mA b 3 mA b 1 mA b 3 mA Output LOW Voltage 54F 10% VCC 74F 10% VCC 05 05 V Min IOL e 20 mA IOL e 24 mA Input HIGH Current 54F 74F 20 0 50 mA Max VIN e 2 7V Input HIGH Current Breakdown Test 54F 74F 100 70 mA Max VIN e 7 0V Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC Input Leakage Test 74F V 00 IID e 1 9 mA All Other Pins Grounded Output Leakage Circuit Current 74F 3 75 mA 00 VIOD e 150 mV All Other Pins Grounded VIN e 0 5V O IOD 08 b1 2 Recognized as a HIGH Signal bs ol VOL V 4 75 IIL Input LOW Current b0 6 mA Max IOZH Output Leakage Current 50 mA Max VOUT e 2 7V IOZL Output Leakage Current b 50 mA Max VOUT e 0 5V IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V IZZ Bus Drainage Test 500 mA 0 0V VOUT e 5 25V ICCZ Power Supply Current 55 mA Max VO e HIGH Z b 60 38 3
TI
Texas Instruments Incorporated
U.S.A
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