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74F399
54F 74F398 54F 74F399 Quad 2-Port Register General Description Features The ’F398 and ’F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flipflops A common Select input determines which of the two 4-bit words is accepted The selected data enters the flipflops on the rising edge of the clock The ’F399 is the 16-pin version of the ’F398 with only the Q outputs of the flip-flops available Y Commercial Y Y Y Package Number Military 74F398PC Select inputs from two data sources Fully positive edge-triggered operation Both true and complement outputs ’F398 Guaranteed 4000V minimum ESD protection ’F399 Package Description N20A 20-Lead (0 300 Wide) Molded Dual-In-Line 54F398DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC 54F398FM (Note 2) W20A 20-Lead Cerpack 74F398SC (Note 1) 54F398LM (Note 2) E20A 54F399DM (Note 2) 20-Lead Ceramic Leadless Chip Carrier Type C N20A 74F399PC 20-Lead (0 300 Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line 74F399SC (Note 1) M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC 74F399SJ (Note 1) M20D 20-Lead (0 300 Wide) Molded Small Outline EIAJ 54F399FM (Note 2) W20A 20-Lead Cerpack 54F399LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Connection Diagrams ’F398 Pin Assignment for LCC Pin Assignment for DIP SOIC and Flatpak TL F 9533 – 5 TL F 9533 – 6 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9533 RRD-B30M75 Printed in U S A 54F 74F398 54F 74F399 Quad 2-Port Register May 1995 Function Table Functional Description The ’F398 and ’F399 are high-speed quad 2-port registers They select four bits of data from either of two sources (Ports) under control of a common Select input (S) The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP) The 4-bit D-type output register is fully edge-triggered The Data inputs (I0x I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation The ’F398 has both Q and Q outputs Inputs Outputs S I0 I1 Q Q I I h h I h X X X X I h L H L H H L H L H e HIGH Voltage Level L e LOW Voltage Level h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X e Immaterial ’F398 only Logic Diagram TL F 9533 – 9 ’F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3
NS
National Semiconductor Corporation 日本ではナショセミと略称されていたが2011年9月23日、米TI社に買収され、同社のシリコンバレー部門となった。
TI
Texas Instruments Incorporated
U.S.A
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