CD74FCT374
BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS739 – JULY 2000
D
D
D
D
D
D
D
D
D
D
E, M, OR SM PACKAGE
(TOP VIEW)
BiCMOS Technology With Low Quiescent
Power
3-State Outputs Drive Bus Lines Directly
Buffered Inputs
Noninverted Outputs
Input/Output Isolation From VCC
Controlled Output Edge Rates
48-mA Output Sink Current
Output Voltage Swing Limited to 3.7 V
SCR Latch-Up-Resistant BiCMOS Process
and Circuit Design
Package Options Include Plastic
Small-Outline (M) and Shrink Small-Outline
(SM) Packages and Standard Plastic (E) DIP
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
description
The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology
and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers.
The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode
drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source
of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during
simultaneous output switching. The output configuration also enhances switching speed and is capable of
sinking 48 mA.
The eight flip-flops enter data into their registers on the low-to-high transition of the clock (CLK). The
output-enable (OE) input controls the 3-state outputs and is independent of the register operation. When OE
is high, the outputs are in the high-impedance state.
A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to drive bus lines without interface or
pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The CD74FCT374 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD74FCT374
BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS739 – JULY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
DC input clamp current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
DC output clamp current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA
Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
Package thermal impedance, θJA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
SM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 2)
MIN
MAX
UNIT
4.75
5.25
V
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
IOL
∆t/∆v
High-level input voltage
2
V
0.8
V
VCC
VCC
V
High-level output current
–15
mA
Low-level output current
48
mA
10
ns/V
Input transition rise or fall rate
0
V
TA
Operating free-air temperature
0
70
°C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
MAX
VIK
VOH
II = –18 mA
IOH = –15 mA
4.75 V
VOL
II
IOL = 48 mA
VI = VCC or GND
4.75 V
5.25 V
VO = VCC or GND
VI = VCC or GND,
5.25 V
ICC
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
Ci
4.75 V
VO = 0
IO = 0
5.25 V
–1.2
2.4
UNIT
V
2.4
V
0.55
V
±0.1
±1
mA
±0.5
±10
mA
–60
–60
mA
5.25 V
8
80
mA
5.25 V
1.6
1.6
mA
10
10
pF
15
pF
VI = VCC or GND
VO = VCC or GND
Co
15
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.
§ This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
POST OFFICE BOX 655303
MAX
–1.2
0.55
IOZ
IOS‡
MIN
• DALLAS, TEXAS 75265
3
