IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
IDT74FCT388915T
70/100/133/150
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x output,
one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Duty cycle distortion < 500ps (max.)
• 32/–16mA drive at CMOS output voltage levels
• VCC = 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC and SSOP packages
The FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low
skew clock distribution for high performance PCs and workstations. One of
the outputs is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of the phase/
frequency detector, charge pump, loop filter and VCO. The VCO is
designed for a 2Q operating frequency range of 40MHz to f2Q Max.
The FCT388915T provides 8 outputs, the Q5 output is inverted from the
Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the
Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the output
path. PLL _EN allows bypassing of the PLL, which is useful in static test
modes. When PLL_EN is low, SYNC input may be used as a test clock. In
this test mode, the input frequency is not limited to the specified range and
the polarity of outputs is complementary to that in normal operation (PLL_EN
= 1). The LOCK output attains logic HIGH when the PLL is in steady-state
phase and frequency lock. When OE/RST is low, all the outputs are put in
high impedance state and registers at Q, Q and Q/2 outputs are reset.
The FCT388915T requires one external loop filter component as
recommended in Figure 3.
FUNCTIONAL BLOCK DIAGRAM
FEED BAC K
SYNC (0)
SYNC (1)
LOCK
0M
u
1x
Phase/Freq.
Detector
Voltage
Controlled
Oscilator
Charge Pum p
LF
REF_SEL
PLL_EN
0
1
M ux
Divide
-By-2
2Q
( ÷ 1)
1M
( ÷ 2)
0
u
x
D
Q
Q
CP
OE/RST
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q/2
R
D
CP
Q1
Q
D
FREQ_SEL
Q0
CP R Q
R
D
CP R
D
CP
R
D
CP R
D
CP R
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
OCTOBER 2008
1
© 2004 Integrated Device Technology, Inc.
DSC-4243/7
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25°C, F = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to +7
V
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
VTERM(4)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +60
mA
Symbol
Parameter
Conditions
Typ.
Max.
Unit
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
5.5
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 5.5V
—
—
±1
µA
IIL
Input LOW Current(4)
VCC = Max.
VI = GND
—
—
±1
µA
IOZH
High Impedance Output Current(4)
VCC = Max.
VI = VCC
—
—
±1
µA
IOZL
(3-State Output Pins)
VIK
Clamp Diode Voltage
IODH
Output Drive Current
VCC = Min., VIN = VIH or VIL, VO =
1.5V(3)
1.5V(3)
IODL
Output Drive Current
VCC = Min., VIN = VIH or VIL, VO =
VOH
Output HIGH Voltage
VCC = Min
VOL
VH
Output LOW Voltage
Input Hysteresis
VCC = Min
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.,VIN = GND or VCC
(Test Mode)
—
—
±1
—
VI = GND
VCC = Min., IIN = –18mA
–0.7
–1.2
V
–36
—
—
mA
—
—
mA
2.4(4)
3.3
—
V
IOL = 32mA
—
50
IOH = –16mA
—
—
0.3
100
0.5
—
V
mV
—
2
6
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. VOH = VCC - 0.6V at rated current.
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