®
IDT54/74FCT821A/B/C
IDT54/74FCT823A/B/C
IDT54/74FCT824A/B/C
IDT54/74FCT825A/B/C
HIGH-PERFORMANCE
CMOS BUS INTERFACE
REGISTERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• Equivalent to AMD’s Am29821-25 bipolar registers in
pinout/function, speed and output drive over full temperature and voltage supply extremes
• IDT54/74FCT821A/823A/824A/825A equivalent to
FAST™ speed
• IDT54/74FCT821B/823B/824B/825B 25% faster than
FAST
• IDT54/74FCT821C/823C/824C/825C 40% faster than
FAST
• Buffered common Clock Enable (EN) and asynchronous
Clear input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
• Substantially lower input current levels than AMD’s
bipolar Am29800 series (5µA max.)
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT800 series is built using an advanced
dual metal CMOS technology.
The IDT54/74FCT820 series bus interface registers are
designed to eliminate the extra packages required to buffer
existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The IDT54/
74FCT821 are buffered, 10-bit wide versions of the popular
‘374 function. The IDT54/74FCT823 and IDT54/74FCT824
are 9-bit wide buffered registers with Clock Enable (EN) and
Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The IDT54/74FCT825 are
8-bit buffered registers with all the ‘823 controls plus multiple
enables (OE1, OE2, OE3) to allow multiuser control of the
interface, e.g., CS, DMA and RD/WR. They are ideal for use
as an output port requiring HIGH IOL/IOH.
All of the IDT54/74FCT800 high-performance interface
family are designed for high-capacitance load drive capability,
while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes and all outputs are
designed for low-capacitance bus loading in high-impedance
state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT824
IDT54/74FCT821/823/825
D0
D0
DN
EN
EN
CLR
DN
CLR
D
CL
Q
D
CP Q
CL
Q
D
CP Q
CL
Q
D
CP Q
CP
Q
CP Q
CP
OE
CL
OE
Y0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
YN
2608 cnv* 01
YN
2608 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1992 Integrated Device Technology, Inc.
Y0
7.19
MAY 1992
DSC-4618/2
1
IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
IDT54/74FCT821/823/825
PRODUCT SELECTOR GUIDE
Device
10-Bit
Non-inverting
9-Bit
Inputs
8-Bit
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
Inverting
OE
PIN DESCRIPTION
I/O
CLR
I
I
CP
I
YI , YI
O
EN
I
OE
I
Description
The D flip-flop data inputs.
For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the QI outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition.
The register three-state outputs.
EN
DI
CP
H
H
L
L
L
H
↑
↑
L
H
Z
Z
H
L
H
L
H
H
L
L
2608 tbl 01
CLR
H
H
54/74FCT824A/B/C
Name
DI
Internal/
Outputs
QI
YI
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
↑
↑
↑
L
L
NC
NC
L
H
L
H
Z
L
Z
NC
Z
Z
L
H
Function
High Z
Clear
Hold
Load
NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-HIGH
Transition, Z = High Impedance
FUNCTION TABLE(1)
IDT54/74FCT824
Clock Enable. When the clock enable
is LOW, data on the D I input is
transferred to the QI output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the QI
outputs do not change state,
regardless of the data or clock input
transitions.
Output Control. When the OE input is
HIGH, the Y I outputs are in the high
impedance state. When the OE input is
LOW, the TRUE register data is
present at the Y I outputs.
Inputs
Internal/
Outputs
QI
YI
OE
EN
DI
CP
H
H
L
L
L
H
↑
↑
H
L
Z
Z
H
L
H
L
H
H
L
L
2608 tbl 10
CLR
H
H
L
L
H
H
H
H
H
H
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
↑
↑
↑
L
L
NC
NC
H
L
H
L
Z
L
Z
NC
Z
Z
H
L
Function
High Z
Clear
Hold
Load
NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-toHIGH Transition, Z = High Impedance
7.19
3
