IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
IDT74FCT88915TT
55/70/100/133
NRND
Product Discontinuance Notice – Last Time Buy Expires on (9/25/2013)
DESCRIPTION:
FEATURES:
Product Assembled
from Die Bank Only
The FCT88915TT uses phase-lock loop technology to lock the frequency
and phase of outputs to the input reference clock. It provides low skew clock
distribution for high performance PCs and workstations. One of the outputs is
fed back to the PLL at the FEEDBACK input resulting in essentially zero delay
across the device. The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The VCO is designed to run optimally between
20MHz and f2Q Max.
The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is
inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs
at half the Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the output path.
PLL _EN allows bypassing of the PLL, which is useful in static test modes. When
PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the
input frequency is not limited to the specified range and the polarity of outputs
is complementary to that in normal operation (PLL_EN = 1). The LOCK output
attains logic high when the PLL is in steady-state phase and frequency lock.
The FCT88915TT requires external loop filter components as recommended in Figure 2.
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 133MHz
• Pin and function compatible with MC88915
• Five non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• Output Skew < 500ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 0.55ns (from tPD max. spec)
• 64/–15mA drive at TTL output voltage levels
• Available in PLCC and SSOP packages
• Not Recommended for New Design
FUNCTIONAL BLOCK DIAGRAM
FEEDBAC K
SYNC (0)
SYNC (1)
LOCK
0M
u
1x
Phase/Freq.
Detector
Voltage
Controlled
Oscilator
C harge Pump
LF
REF_SEL
PLL_EN
0
1
Mux
2Q
( 1)
Divide
-By-2
1M
u
0x
( 2)
D
CP
Q
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
D
FREQ_SEL
Q0
R Q
Q5
Q
Q/2
CP R
RST
D
CP R
D
CP
R
D
CP
R
D
CP
R
D
CP R
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
MAY 2013
1
© 2013 Integrated Device Technology, Inc.
DSC-4245/4
IDT74FCT88915TT
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
CAPACITANCE (TA = +25°C, f = 1.0MHz)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
VTERM(3)
TA
TBIAS
TSTG
IOUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Operating Temperature
Temperature Under Bias
StorageTemperature
DC Output Current
Max.
–0.5 to 7
–0.5 to VCC+0.5
0 to +70
–55 to +125
–55 to +125
–60 to 120
Parameter(1)
Symbol
Unit
V
V
°C
°C
°C
mA
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SYNC INPUT TIMING REQUIREMENTS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Outputs and I/O terminals.
Symbol
TRISE/FALL
Frequency
Duty Cycle
Parameter
Rise/Fall Times, SYNC inputs
(0.8V to 2.0V)
Input Frequency, SYNC Inputs
Input Duty Cycle, SYNC Inputs
Min.
—
Max.
3
Unit
ns
10
25%
2Q fmax
75%
MHz
—
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 5.0V ±5%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current
VCC = Max.
VI = VCC
—
—
±1
µA
IIL
Input LOW Current
VI = GND
—
—
±1
µA
VIK
Clamp Diode Voltage
—
–0.7
–1.2
V
VIH
Input Hysteresis
—
100
—
mV
VOH
Output HIGH Voltage
VCC = Min.
IOH = –15mA
2.4
3.5
—
V
VOL
Output LOW Voltage
VCC = Min.
IOL = 64mA
—
0.2
0.55
V
ICCL
ICCH
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
(Test mode, LF connected to GND)
—
2
4
mA
VCC = Min., IIN = –18mA
—
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
3
