MC74HC04A
Hex Inverter
High−Performance Silicon−Gate CMOS
The MC74HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The device consists of six three−stage inverters.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 36 FETs or 9 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
A2
A3
1
2
3
4
5
6
Y1
A5
A6
9
8
11
10
13
12
1
HC04AG
AWLYWW
1
14
14
1
HC
04A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Y2
FUNCTION TABLE
Y3
Inputs
Y
L
H
Y4
Outputs
A
Y=A
A4
14
A
L, WL
Y, YY
W, WW
G or G
LOGIC DIAGRAM
A1
14
SOIC−14
D SUFFIX
CASE 751A
H
L
Y5
ORDERING INFORMATION
Y6
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Pinout: 14−Lead Packages (Top View)
VCC
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 14
1
Publication Order Number:
MC74HC04A/D
MC74HC04A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Guaranteed Limit
VCC
V
Condition
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1V or VCC −0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1V or VCC − 0.1V
|Iout| ≤ 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| ≤ 20mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Vin =VIH or VIL
VOL
Maximum Low−Level Output
Voltage
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
Vin = VIH or VIL
|Iout| ≤ 20mA
Vin = VIH or VIL
|Iout| ≤ 2.4mA
|Iout| ≤ 4.0mA
|Iout| ≤ 5.2mA
V
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
6.0
1.0
10
40
mA
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Guaranteed Limit
VCC
V
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
Maximum Input Capacitance
Typical @ 25°C, VCC = 5.0 V
CPD
20
Power Dissipation Capacitance (Per Inverter)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
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3
2f
+ ICC VCC .
pF
