INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jun 10
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
74HC112D;
74HCT112D
74HC112DB;
74HCT112DB
SO16
SSOP16
74HC112N;
74HCT112N
74HC112PW;
74HCT112PW
DIP16
TSSOP16
DESCRIPTION
VERSION
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 13
1CP, 2CP
clock input (HIGH-to-LOW, edge triggered)
2, 12
1K, 2K
data inputs; flip-flops 1 and 2
3, 11
1J, 2J
data inputs; flip-flops 1 and 2
4, 10
1SD, 2SD
set inputs (active LOW)
5, 9
1Q, 2Q
true flip-flop outputs
6, 7
1Q, 2Q
complement flip-flop outputs
8
GND
ground (0 V)
15, 14
1RD, 2RD
reset inputs (active LOW)
16
VCC
positive supply voltage
Fig.1 Pin configuration.
1998 Jun 10
Fig.2 Logic symbol.
3
Fig.3 IEC logic symbol.