MC74HC132A
Quad 2−Input NAND Gate
with Schmitt−Trigger Inputs
High−Performance Silicon−Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
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MARKING
DIAGRAMS
14
Features
•
•
•
•
•
•
•
•
PDIP−14
N SUFFIX
CASE 646
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
Chip Complexity: 72 FETs or 18 Equivalent Gates
Pb−Free Packages are Available
MC74HC132AN
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
HC132AG
AWLYWW
1
14
HC
132A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
A1
1
14
VCC
B1
2
13
B4
Y1
3
12
A4
A2
4
11
Y4
B2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
1
14
SOEIAJ−14
F SUFFIX
CASE 965
74HC132A
ALYWG
1
A
= Assembly Location
L, WL = Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
Figure 1. Pin Assignment
FUNCTION TABLE
Inputs
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 12
1
Publication Order Number:
MC74HC132A/D
MC74HC132A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Positive DC Supply Voltage
*0.5 to )7.0
V
VIN
Digital Input Voltage
*0.5 to )7.0
V
VOUT
DC Output Voltage
*0.5 to )7.0
*0.5 to VCC )0.5
V
IIK
Input Diode Current
*20
mA
IOK
Output Diode Current
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$75
mA
IGND
DC Ground Current per Ground Pin
$75
mA
TSTG
Storage Temperature Range
*65 to )150
_C
260
_C
)150
_C
14−PDIP
14−SOIC
14−TSSOP
78
125
170
_C/W
PDIP
SOIC
TSSOP
750
500
450
mW
Output in 3−State
High or Low State
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Level 1
Flammability Rating
Oxygen Index: 30% − 35%
UL 94 V0 @ 0.125 in
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u100
u500
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85_C (Note 4)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
5. For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
ÎÎÎ
Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎ Î Î
Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
2.0
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 3)
V
VCC
V
)125
_C
−
TA
6.0
0
*55
DC Input Voltage, Output Voltage (Referenced to GND)
No Limit
(Note 6)
ns
6. When VIN X 0.5 VCC, ICC >> quiescent current.
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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