MC74HC138A
1-of-8 Decoder/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC138A decodes a three−bit Address to one−of−eight
active−low outputs. This device features three Chip Select inputs, two
active−low and one active−high to facilitate the demultiplexing,
cascading, and chip−selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
16
1
1
Features
•
•
•
•
•
•
•
•
MC74HC138AN
AWLYYWWG
16
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
Chip Complexity: 100 FETs or 29 Equivalent Gates
Pb−Free Packages are Available*
SOIC−16
D SUFFIX
CASE 751B
16
1
HC138AG
AWLYWW
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
HC
138A
ALYWG
G
1
16
16
1
SOEIAJ−16
F SUFFIX
CASE 966
74HC138A
ALYWG
1
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 10
1
Publication Order Number:
MC74HC138A/D
MC74HC138A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
Plastic DIP†
SOIC Package†
TSSOP Package†
_C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating − Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 .W/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Unit
2.0
DC Supply Voltage (Referenced to GND)
Max
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
TA
tr, tf
Input Rise and Fall Time
(Figure 2)
0
VCC
V
– 55
Operating Temperature, All Package Types
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
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3
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
