IDT79R3051™ , 79R3051E
IDT79R3052™ , 79R3052E
IDT79R3051/79R3052
RISControllers™
Integrated Device Technology, Inc.
— On-chip DMA arbiter
— Bus Interface minimizes design complexity
• Single clock input with 40%-60% duty cycle
• 35 MIPS, over 64,000 Dhrystones at 40MHz
• Low-cost 84-pin PLCC packaging
FEATURES:
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
— IDT79R3000A /IDT79R3001 RISC Integer CPU
— R3051 features 4KB of Instruction Cache
— R3052 features 8KB of Instruction Cache
— All devices feature 2kB of Data Cache
— “E” Versions (Extended Architecture) feature full
function Memory Management Unit, including 64entry Translation Lookaside Buffer (TLB)
— 4-deep write buffer eliminates memory write stalls
— 4-deep read buffer supports burst refill from slow
memory devices
Clk2xIn
Clock
Generator
Unit
• Flexible bus interface allows simple, low-cost designs
• 20, 25, 33, and 40MHz operation
• Complete software support
— Optimizing compilers
— Real-time operating systems
— Monitors/debuggers
— Floating Point Software
— Page Description Languages
BrCond(3:0)
Master Pipeline Control
System Control
Coprocessor
Integer
CPU Core
Exception/Control
Registers
General Registers
(32 x 32)
Memory Management
Registers
ALU
Shifter
Int(5:0)
Mult/Div Unit
Translation
Lookaside Buffer
(64 entries)
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
Instruction
Cache
(8kB/4kB)
32
Data
Cache
(2kB)
Data Bus
Bus Interface Unit
4-deep
Write
Buffer
4-deep
Read
Buffer
Address/
Data
DMA
Arbiter
DMA
Ctrl
BIU
Control
Rd/Wr
Ctrl
SysClk
2874 drw 01
Figure 1. R3051 Family Block Diagram
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©2001 Integrated Device Technology, Inc.
OCTOBER 2001
5.3
DSC-3000/6
1
