80960KB
80960KB
EMBEDDED 32-BIT MICROPROCESSOR
WITH INTEGRATED FLOATING-POINT UNIT
s High-Performance Embedded
s Built-in Interrupt Controller
Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
s 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
s Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
s 4 Gigabyte, Linear Address Space
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
s Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
s 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
s On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point
Standard
— Four 80-Bit Registers
— 13.6 Million Whetstones/s (Single
Precision) at 25 MHz
s Pin Compatible with 80960KA
FOUR
80-BIT FP
REGISTERS
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
80-BIT
FPU
32-BIT
BUS CONTROL
LOGIC
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICROINSTRUCTION
SEQUENCER
MICROINSTRUCTION
ROM
32-BIT
BURST
BUS
Figure 1. The 80960KB Processor’s Highly Parallel Architecture
© INTEL CORPORATION, 2004
August, 2004
Order Number: 270565-008
