a
FEATURES
16-Bit Sigma-Delta ADC
468.75 kHz Output Word Rate (OWR)
No Missing Codes
Low-Pass Digital Filter
High Speed Serial Interface
Linear Phase
229.2 kHz Input Bandwidth
Power Supplies: AVDD, DVDD: +5 V ؎ 5%
Standby Mode (70 W)
Parallel Mode (12-Bit/312.5 kHz OWR)
CMOS 16-Bit,
468.75 kHz, Sigma-Delta ADC
AD7721
FUNCTIONAL BLOCK DIAGRAM
AGND
AGND
DVDD
AVDD
DGND
DGND
AD7721
DSUBST
12-BIT A/D CONVERTER
VIN1
⌺-⌬
MODULATOR
VIN2
REFIN
FIR
FILTER
DVAL/SYNC
CS
CLK
RD
WR
DRDY
STBY/DB0
SDATA/DB11
CAL/DB1
CONTROL LOGIC
UNI/DB2
GENERAL DESCRIPTION
The AD7721 is a complete low power, 12-/16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input of 0 V to 2.5 V or ± 1.25 V. The analog input
is continuously sampled by an analog modulator at twice the
clock frequency eliminating the need for external sample-andhold circuitry. The modulator output is processed by two finite
impulse response (FIR) digital filters in series. The on-chip
filtering reduces the external antialias requirements to first order
in most cases. Settling time for a step input is 97.07 µs while
the group delay for the filter is 48.53 µs when the master clock
equals 15 MHz.
The AD7721 can be operated with input bandwidths up to
229.2 kHz. The corresponding output word rate is 468.75 kHz.
The part can be operated with lower clock frequencies also.
The sample rate, filter corner frequency and output word rate
will be reduced also, as these are proportional to the external
clock frequency. The maximum clock frequencies in parallel
mode and serial mode are 10 MHz and 15 MHz respectively.
RFS/DB10
DB9
DB3
DB4
SYNC/ DB6
DB5
SCLK/ DB8
DB7
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by onchip calibration of offset and gain. This calibration procedure
minimizes the part’s zero-scale and full-scale errors.
The output data is accessed from the output register through a
serial or parallel port. This offers easy, high speed interfacing to
modern microcontrollers and digital signal processors. The
serial interface operates in internal clocking (master) mode, the
AD7721 providing the serial clock.
CMOS construction ensures low power dissipation while a
power-down mode reduces the power consumption to only
100 µW.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
