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AD7835AP

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LC2MOS Quad 14-Bit DACs AD7834/AD7835 into one via DIN, SCLK, and FSYNC. The AD7834 has five dedicated package address pins, PA0 to PA4, that can be wired to AGND or VCC to permit up to 32 AD7834s to be individually addressed in a multipackage application. FEATURES Four 14-bit DACs in one package AD7834—serial loading AD7835—parallel 8-bit/14-bit loading Voltage outputs Power-on reset function Maximum/minimum output voltage range of ±8.192 V Maximum output voltage span of 14 V Common voltage reference inputs User-assigned device addressing Clear function to user-defined voltage Surface-mount packages AD7834—28-lead SOIC and PDIP AD7835—44-lead MQFP and PLCC The AD7835 can accept either 14-bit parallel loading or doublebyte loading, where right-justified data is loaded in one 8-bit byte and one 6-bit byte. Data is loaded from the external bus into one of the input latches under the control of the WR, CS, BYSHF, and DAC channel address pins, A0 to A2. GENERAL DESCRIPTION With each device, the LDAC signal is used to update all four DAC outputs simultaneously, or individually, on reception of new data. In addition, for each device, the asynchronous CLR input can be used to set all signal outputs, VOUT1 to VOUT4, to the user-defined voltage level on the device sense ground pin, DSG. On power-on, before the power supplies have stabilized, internal circuitry holds the DAC output voltage levels to within ±2 V of the DSG potential. As the supplies stabilize, the DAC output levels move to the exact DSG potential (assuming CLR is exercised). The AD7834 and AD7835 contain four 14-bit DACs on one monolithic chip. The AD7834 and AD7835 have output voltages in the range ±8.192 V with a maximum span of 14 V. The AD7834 is available in a 28-lead 0.3" SOIC package and a 28-lead 0.6" PDIP package, and the AD7835 is available in a 44-lead MQFP package and a 44-lead PLCC package. APPLICATIONS Process control Automatic test equipment General-purpose instrumentation The AD7834 is a serial input device. Data is loaded in 16-bit format from the external serial bus, MSB first after two leading 0s, FUNCTIONAL BLOCK DIAGRAMS AD7834 PAEN PA3 DAC 1 LATCH AD7835 DAC 1 ×1 CONTROL LOGIC AND ADDRESS DECODE PA4 INPUT REGISTER 2 DAC 2 LATCH DB0 ×1 INPUT REGISTER 3 DAC 3 LATCH SERIAL-TOPARALLEL CONVERTER INPUT REGISTER 4 DAC 4 LATCH VOUT 3 A1 AGND DGND LDAC INPUT REGISTER 3 DSG Figure 1. AD7834 ADDRESS DECODE A2 VOUT 4 CLR SCLK DAC 2 LATCH DAC 3 LATCH INPUT REGISTER 4 DAC 4 LATCH DAC 1 ×1 VOUT1 ×1 VOUT2 ×1 VOUT3 DAC 2 DAC 3 A0 DAC 4 ×1 DAC 1 LATCH WR CS ×1 VREF (–)A VREF (+)A DSGA 14 INPUT BUFFER DAC 3 FSYNC DIN VOUT 2 VSS INPUT REGISTER 2 VOUT 1 DAC 2 VDD INPUT REGISTER 1 BYSHF 01006-001 PA2 INPUT REGISTER 1 VCC VREF (–) VREF (+) VSS DB13 PA0 PA1 VDD DAC 4 ×1 VOUT4 CLR AGND DGND LDAC VREF (–)B VREF (+)B DSGB 01006-002 VCC Figure 2. AD7835 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.

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