14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
AD9641
Data Sheet
FEATURES
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO SCLK CSB
DRVDD
SPI
AD9641
PROGRAMMING DATA
DATA SERIALIZER,
ENCODER,
AND CML DRIVERS
VIN+
ADC
VIN–
VCM
REFERENCE
DOUT+
DOUT–
DSYNC+
DSYNC–
DATA RATE
MULTIPLIER
DUTY CYCLE
STABILIZER
MULTICHIP
SYNC
AGND
SYNC
CLK+
DIVIDE-BY-1
TO
DIVIDE-BY-8
PDWN
CLK–
DRGND
09210-001
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Figure 1.
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
The AD9641 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
GENERAL DESCRIPTION
This product is protected by a U.S. patent.
The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641 is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
PRODUCT HIGHLIGHTS
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
1.
2.
3.
4.
5.
An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
Operation is from a single 1.8 V power supply.
The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), controlling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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