PRELIMINARY
Am29030™ and Am29035™
RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache
Advanced
Micro
Devices
Am29030 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS
Full 32-bit architecture
8-, 16-, or 32-bit ROM interface
26 million instructions per second (MIPS)
sustained at 33 MHz
64-entry Memory Management Unit on-chip
8-Kbyte, two-way set-associative instruction
cache
On-chip timer facility
Fully pipelined
192 general-purpose registers
33- and 25-MHz operating frequencies
Three-address instruction architecture
Scalable Clocking™ technology
Master/slave chip/output checking
Programmable 16- or 32-bit data bus width
CMOS technology/TTL-compatible
Software compatible with Am29005™ and
Am29000® microprocessors
4-Gbyte virtual address space with demand
paging
Advanced debugging support
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and Boundary
Scan Architecture implementation
Streamlined system interface for simplified,
high-frequency operation
Burst-mode and page-mode access support
Am29035 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS
The Am29035™ microprocessor is similar to the Am29030™ microprocessor except for the following differences:
4-Kbyte, direct-mapped instruction cache
12 million instructions per second (MIPS)
sustained at 16 MHz
16-MHz operating frequency
SIMPLIFIED BLOCK DIAGRAM
Address
Am29030 and Am29035
RISC Microprocessors
with 8Kbyte/4Kbyte
Instruction Cache
Instruction/Data
32 or 16
32
32 or 16
8, 16, or 32
Address
Instruction/
Data
ROM
Address
Instruction/
Data
RAM
Instruction/Data
32 or 16
Instruction/Data
Publication# 18150 Rev. A Amendment /0
Issue Date: August 1993. WWW: 5/4/95
