FINAL
Am79865/Am79866A
Physical Data Transmitter/Physical Data Receiver
DISTINCTIVE CHARACTERISTICS
s Fully compliant with ANSI X3T9.5 FDDI,
TP-FDDI, and 100BASE-TX/FX PHY standards
s The on-chip Phase-Locked-Loop (PLL) only
requires an external frequency reference
s Provides data and clock recovery functions for
FDDI and Fast Ethernet applications
s 125 MBaud (100 Mbps) serial link data rate
s Parallel input to the PDT is a 5-bit encoded NRZ
symbol clocked by LSCLK
s Parallel output from the PDR is a 5-bit
unframed NRZ symbol clocked by RSCLK
s Dedicated pins provide electrical loopback
data path
s 20-pin Plastic Leaded Chip Carrier (PLCC)
s Single +5 V power supply operation
s Interfaces to fiber or copper media
GENERAL DESCRIPTION
The Physical Data Transmitter (Am79865) and the
Physical Data Receiver (Am79866) devices provide
clock recovery/generation functions meeting the requirements of FDDI, TP-FDDI, and 100BASE-TX PHY
standards.
The PDT and PDR devices are part of the SUPERNET
2 FDDI Physical Layer Protocol chip set which also includes the Physical Layer Controller with Scrambler
(PLC-S). The PLC-S (Am79C864A), PDT and PDR devices are collectively known as the AmPHY. The PLC-S
performs the FDDI physical layer functions which
includes, among others, the 4B5B encoding and
decoding.
The PDT converts encoded symbols into a serial NRZI
data stream. The on-chip PLL generates a bit rate clock
from the LSCLK reference.
The PDR uses a built-in clock recovery PLL to extract
clock information from the received data stream. The
recovered clock is used for serial-to-parallel data
conversion.
Publication# 15451 Rev: D Amendment/0
Issue Date: June 1996
