PRELIMINARY
Am79C961
PCnetTM-ISA+ Jumperless Single-Chip Ethernet Controller
for ISA
Advanced
Micro
Devices
DISTINCTIVE CHARACTERISTICS
s Single-chip Ethernet controller for the Industry
Standard Architecture (ISA) and Extended
Industry Standard Architecture (EISA) buses
s Look Ahead Packet Processing (LAPP) allows
protocol analysis to begin before end of
receive frame
s Supports IEEE 802.3/ANSI 8802-3 and Ethernet
standards
s Supports 4 DMA channels on chip
s Direct interface to the ISA or EISA bus
s Supports 16 boot PROM locations
s Software compatible with AMD’s Am7990
LANCE register and descriptor architecture
s Provides integrated Attachment Unit Interface
(AUI) and 10BASE-T transceiver with 2 modes
of port selection:
s Low power, CMOS design with sleep mode
allows reduced power consumption for critical
battery powered applications
s Supports 16 I/O locations
— Automatic selection of AUI or 10BASE-T
— Software selection of AUI or 10BASE-T
s Individual 136-byte transmit and 128-byte
receive FIFOs provide packet buffering for
increased system latency, and support the
following features:
s Automatic Twisted Pair receive polarity
detection and automatic correction of the
receive polarity
— Automatic retransmission with no FIFO
reload
s Supports bus-master and shared-memory
architectures to fit in any PC application
— Automatic receive stripping and transmit
padding (individually programmable)
— Automatic runt packet rejection
— Automatic deletion of received collision
frames
s Dynamic transmit FCS generation programmable on a frame-by-frame basis
s Single +5 V power supply
s Internal/external loopback capabilities
s Supports 8K, 16K, 32K, and 64K Boot PROMs
or Flash for diskless node applications
s Supports Microsoft’s Plug and Play System
configuration for jumperless designs
s Supports staggered AT bus drive for reduced
noise and ground bounce
s Supports 8 interrupts on chip
s Supports edge and level-sensitive interrupts
s DMA Buffer Management Unit for reduced CPU
intervention which allows higher throughput by
by-passing the platform DMA
s JTAG Boundary Scan (IEEE 1149.1) test access
port interface for board level production test
s Integrated Manchester Encoder/Decoder
s Supports the following types of network
interfaces:
— AUI to external 10BASE2, 10BASE5,
10BASE-T or 10BASE-F MAU
— Internal 10BASE-T transceiver with Smart
Squelch to Twisted Pair medium
s Supports LANCE General Purpose Serial
Interface (GPSI)
s 132-pin PQFP package
GENERAL DESCRIPTION
The PCnet-ISA+ controller, a single-chip Ethernet controller, is a highly integrated system solution for the
PC-AT Industry Standard Architecture (ISA ) architecture. It is designed to provide flexibility and compatibility
with any existing PC application. This highly integrated
132-pin VLSI device is specifically designed to reduce
parts count and cost, and addresses applications where
higher system throughput is desired. The PCnet-ISA+
Publication# 18183 Rev. B
Issue Date: April 1994
Amendment /0
controller is fabricated with AMD’s advanced low-power
CMOS process to provide low standby current for power
sensitive applications.
The PCnet-ISA+ controller is a DMA-based device with a
dual architecture that can be configured in two different
operating modes to suit a particular PC application. In
the Bus Master Mode all transfers are performed using
This document contains information on a product under development at Advanced Micro Devices, Inc.
The information is intended to help you to evaluate this product. AMD reserves the right to change or
discontinue work on this proposed product without notice.
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