September 2001
AS7C256
AS7C3256
®
5V/3.3V 32K X 8 CMOS SRAM (Common I/O)
Features
• Very low power consumption: STANDBY
• AS7C256 (5V version)
• AS7C3256 (3.3V version)
• Industrial and commercial temperature
• Organization: 32,768 words × 8 bits
• High speed
- 22 mW (AS7C256) / max CMOS I/O
- 7.2 mW (AS7C3256) / max CMOS I/O
• Easy memory expansion with CE and OE inputs
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 12/15/20 ns address access time
- 6, 7, 8 ns output enable access time
- 300 mil PDIP
- 300 mil SOJ
- 8 × 13.4 mm TSOP 1
• Very low power consumption: ACTIVE
- 660mW (AS7C256) / max @ 12 ns
- 216mW (AS7C3256) / max @ 12 ns
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
28-pin TSOP 1 (8×13.4 mm)
VCC
28-pin DIP, SOJ (300 mil)
GND
256 X 128 X 8
Array
(262,144)
Sense amp
I/O7
Row decoder
A0
A1
A2
A3
A4
A5
A6
A14
I/O0
Column decoder
WE
Control
circuit
A14
A12
A7
A6
$
A4
A3
A2
A1
A0
I/O0
Note: This part is compatible with both pin numbering ,2
,2
conventions used by various manufacturers.
GND
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(22)
(23)
(24)
(25)
(26)
(27)
(28) AS7C256
(1) AS7C3256
(2)
(3)
(4)
(5)
(6)
(7)
(21) 28
(20) 27
(19) 26
(18) 25
(17) 24
(16) 23
(15) 22
(14) 21
(13) 20
(12) 19
(11) 18
(10) 17
(9) 16
(8) 15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AS7C256
AS7C3256
Input buffer
VCC
WE
A13
$
$
A11
OE
A10
CE
I/O7
,2
I/O5
I/O4
,2
OE
CE
A
7
A
8
A A A A A
9 10 11 12 13
Selection guide
-12
-15
-20
Unit
Maximum address access time
12
15
20
ns
Maximum output enable access time
6
7
8
ns
AS7C256
120
115
110
mA
AS7C3256
60
55
50
mA
AS7C256
4
4
4
mA
AS7C3256
2
2
2
mA
Maximum operating current
Maximum CMOS standby current
9/18/01; v.1.6
Alliance Semiconductor
P. 1 of 9
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