BSI
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
FEATURES
BS62LV1024
• Easy expansion with CE2, CE1, and OE options
DESCRIPTION
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70
70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
The BS62LV1024 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1024 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1024 is available in JEDEC standard 32 pin 450mil Plastic
SOP, 300mil Plastic SOJ , 600mil Plastic DIP, 8mmx13.4mm STSOP,
8mmx13.4mm Reverse STSOP and 8mmx20mm TSOP.
PRODUCT FAMILY
PRODUCT
F A M ILY
O P E R AT IN G
T E M P E R AT U R E
Vcc
RANGE
SPEED
(n s )
P O W E R D IS S IP AT IO N
S ta n d b y
O p e r a tin g
V cc=3V
B S 6 2 LV 1 0 2 4 S C
B S 6 2 LV 1 0 2 4 T C
B S 6 2 LV 1 0 2 4 S T C
B S 6 2 LV 1 0 2 4 P C
B S 6 2 LV 1 0 2 4 J C
0 O C to + 7 0
O
( Ic c S B 1 , M a x )
V cc=5V V cc=3V
PKG TYPE
(Ic c , M a x )
V cc=5V
V cc=3V
C
2 .4 V ~ 5 .5 V
70
3 .0 u A
1 .0 u A
35m A
20m A
O
2 .4 V ~ 5 .5 V
70
5 .0 u A
1 .5 u A
40m A
25m A
B S 6 2 LV 1 0 2 4 R C
B S 6 2 LV 1 0 2 4 S I
B S 6 2 LV 1 0 2 4 T I
B S 6 2 LV 1 0 2 4 S T I
B S 6 2 LV 1 0 2 4 P I
B S 6 2 LV 1 0 2 4 J I
-4 0 O C to + 8 5
C
B S 6 2 LV 1 0 2 4 R I
PIN CONFIGURATIONS
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
BS62LV1024SC 27
BS62LV1024SI 26
BS62LV1024PC
25
BS62LV1024PI
24
BS62LV1024JC
BS62LV1024JI 23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV1024TC
BS62LV1024STC
BS62LV1024TI
BS62LV1024STI
•
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
BLOCK DIAGRAM
•
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
S O P -3 2
T S O P -3 2
S T S O P -3 2
P D IP -3 2
S O J -3 2
R e ve rs e
S T S O P -3 2
S O P -3 2
T S O P -3 2
S T S O P -3 2
P D IP -3 2
S O J -3 2
R e ve rs e
S T S O P -3 2
BS62LV1024RC
BS62LV1024RI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
Address
Input
Buffer
20
Row
1024
Memory Array
1024 x 1024
Decoder
1024
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
CE2
CE1
WE
OE
Vdd
Gnd
8
8
Data
Input
Buffer
Data
Output
Buffer
Column I/O
8
8
Write Driver
Sense Amp
128
Column Decoder
14
Control
Address Input Buffer
A5 A4 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV1024
1
Revision 2.4
Jan.
2004
