327
CY7C1358A/
GVT7164T18
64K x 18 Synchronous Cache Tag RAM
Pipelined Output
Features
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Functional Description
Fast match times: 4.5, 5.0, 6.0, and 7.0 ns
Fast clock speed: 133, 100, 83, and 75 MHz
Fast OE access times: 4.5 ns and 5.0 ns
Pipelined data comparator
Data input register load control by DEN
3.3V –5% and +10% power supply
5V tolerant inputs except I/Os
Clamp diodes to VSS at all inputs and outputs
Common data inputs and data outputs
Two chip enables for depth expansion
Address, data, and control registers
Internally self-timed Write cycle
Automatic power-down for portable applications
Low profile 100-pin TQFP package
The Cypress Synchronous SRAM family employs high-speed,
low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.
The GVT7164T18 SRAM integrates 65,536 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a 18-bit
comparator for tag compare operation. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE
and CE1), Write Enable (WE), and Data Input Enable (DEN).
Asynchronous inputs include the Output Enable (OE) and the
Match Output Enable (MOE). The Data Outputs (Q) and Match
Output (MATCH), enabled by OE and MOE respectively, are
also asynchronous.
Data inputs are registered with Data Input Enable (DEN) and
Chip Enable pins (CE, CE1). The outputs of the data input
registers are compared with data in the memory array and a
match signal is generated. The match output is gated into a
pipeline register and released to the match output pin at the
next rising edge of Clock (CLK).
The GVT7164T18 operates from a +3.3V power supply. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 2 MB secondary cache.
Selection Guide
7C1358A-133
7164T18-4
7C1358A-100
7164T18-5
7C1358A-83
7164T18-6
7C1358A-75
7164T18-7
Maximum Access Time (ns)
4.5
5.0
6.0
7.0
Maximum Operating Current (mA)
300
240
220
200
Maximum CMOS Standby Current (mA)
20
20
20
20
Cypress Semiconductor Corporation
Document #: 38-05121 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised January 19, 2003
