H
EE
GEN FR
ALO
CAT28C64B
64K-Bit CMOS PARALLEL EEPROM
LE
A D F R E ETM
FEATURES
s Fast read access times:
s Commercial, industrial and automotive
– 90/120/150ns
temperature ranges
s Low power CMOS dissipation:
s Automatic page write operation:
– Active: 25 mA max.
– Standby: 100 µA max.
– 1 to 32 bytes in 5ms
– Page load timer
s Simple write operation:
s End of write detection:
– On-chip address and data latches
– Self-timed write cycle with auto-clear
– Toggle bit
– DATA polling
s Fast write cycle time:
s 100,000 program/erase cycles
– 5ms max.
s 100 year data retention
s CMOS and TTL compatible I/O
s Hardware and software write protection
DESCRIPTION
The CAT28C64B is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDECapproved 28-pin DIP, TSOP, SOIC, or, 32-pin PLCC
package .
The CAT28C64B is a fast, low power, 5V-only CMOS
Parallel EEPROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write
protection.
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
ROW
DECODER
VCC
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
CE
OE
WE
8,192 x 8
EEPROM
ARRAY
CONTROL
LOGIC
I/O BUFFERS
TIMER
A0–A4
32 BYTE PAGE
REGISTER
DATA POLLING
AND
TOGGLE BIT
ADDR. BUFFER
& LATCHES
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I/O0–I/O7
COLUMN
DECODER
1
Doc. No. 1011, Rev. F
