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CY7B136-15JC

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仕様・特性

fax id: 5208 1CY 7B1 46 CY7B136 CY7B146 2K x 8 Dual-Port Static RAM Features • • • • • • • • 0.8-micron BiCMOS for high performance Automatic power-down TTL compatible Capable of withstanding greater than 2001V electrostatic discharge Fully asynchronous operation Master CY7B136 easily expands data bus width to 16 or more bits using slave CY7B146 BUSY output flag on CY7B136; BUSY input on CY7B146 INT flag for port-to-port communication Functional Description The CY7B136 and CY7B146 are high-speed BiCMOS 2K by 8 dual-port static RAMS. Two ports are provided to permit independent access to any location in memory. The CY7B136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7B146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the right port and 7FE for the left port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7B136/CY7B146 are available in 52-lead PLCC. Logic Block Diagram R/W L CE L R/WR CE R OE L A10L OER A10R A7L I/O0L A7R I/O 0R COL SEL I/O 7L BUSYL COLUMN I/O COLUMN I/O I/O 7R [1] [1] BUSYR A6L MEMORY ARRAY ROW SELECT A0L ROW SELECT BUSYL [2] A0L CE L OE L R/WL A6R A0R A10R A10L INT L COL SEL ARBITRATION LOGIC (7B136 ONLY) AND INTERRUPTLOGIC A0R CER OER R/W R BUSYR INT R [2] B136-1 Notes: 1. CY7B136 (Master): BUSY an open drain output and requires a pull-up resistor. CY7B146 (Slave): BUSY is an input. 2. Open drain outputs; pull-up resistor required Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 1995 – Revised July 1995

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