CY7B144
CY7B145
8K x 8/9 DualĆPort Static RAM
with Sem, Int, Busy
Features
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Each port has independent control pins:
chip enable (CE), read or write enable
(R/W), and output enable (OE). Two
flags, BUSY and INT, are provided on
each port. BUSY signals that the port is
trying to access the same location currentĆ
ly being accessed by the other port. The
interrupt flag (INT) permits communicaĆ
tion between ports or systems by means of
a mail box. The semaphores are used to
pass a flag, or token, from one port to the
other to indicate that a shared resource is
in use. The semaphore logic is comprised
of eight shared latches. Only one side can
control the latch (semaphore) at any time.
Control of a semaphore indicates that a
shared resource is in use. An automatic
powerĆdown feature is controlled indeĆ
pendently on each port by a chip enable
(CE) pin or SEM pin.
Functional Description
The CY7B144 and CY7B145 are highĆ
speed BiCMOS 8K x 8 and 8K x 9 dualĆ
port static RAMs. Various arbitration
schemes are included on the CY7B144/5
to handle situations when multiple procesĆ
sors access the same piece of data. Two
ports are provided permitting indepenĆ
dent, asynchronous access for reads and
writes to any location in memory. The
CY7B144/5 can be utilized as a standaĆ
lone 64ĆKbit dualĆport static RAM or
multiple devices can be combined in order
to function as a 16/18Ćbit or wider master/
slave dualĆport static RAM. An M/S pin is
provided for implementing 16/18Ćbit or
wider memory applications without the
need for separate master and slave devices
or additional discrete logic. Application
areas include interprocessor/multiprocesĆ
sor designs, communications status bufferĆ
ing, and dualĆport video/graphics memory.
0.8Ćmicron BiCMOS for high
performance
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HighĆspeed access
Ċ 15
Ċ 25
ns (commercial)
ns (military)
Automatic powerĆdown
Fully asynchronous operation
Master/Slave select pin allows bus
width expansion to 16/18 bits or more
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Busy arbitration scheme provided
Semaphores included to permit softĆ
ware handshaking between ports
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INT flag for portĆtoĆport
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Available in 68Ćpin LCC/PLCC, 64Ćpin
communication
and 80Ćpin TQFP
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TTL compatible
Pin compatible and functionally
equivalent to IDT7005 and IDT7015
The CY7B144 and CY7B145 are available
in 68Ćpin LCCs, PLCCs, 64Ćpin (CY7B144)
and 80Ćpin TQFP (CY7B145).
Logic Block Diagram
R/WL
R/WR
CEL
CER
OEL
OER
A12L
A12R
A10R
A10L
(7B145) I/O8L
I/O8R (7B145)
I/O7L
COL
COLUMN
I/O0L
COLUMN
I/O
SEL
I/O
I/O7R
COL
SEL
I/O0R
BUSYL[1, 2]
BUSYR[1, 2]
A9L
A9R
ROW
MEMORY
ROW
SELECT
ARRAY
SELECT
A0L
A0R
A12R
A12L
A0 L
A0R
INTERRUPT
SEMAPHORE
ARBITRATION
CE L
CER
OE L
OER
R/WL
R/WR
SEML
SEMR
INTL[2]
INTR[2]
B144-1
M/S
Notes:
1.
BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
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2.
3901 North First Street
1
Master: pushĆpull output and requires no pullĆup resistor.
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San Jose
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CA 95134
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408-943-2600
December 1990 - Revised April 1995
