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CY7C008-20AC
CY7C008/009 CY7C018/01964K/128K x 8/9 Dual-Port Static RAM CY7C008/009 CY7C018/019 64K/128K x 8/9 Dual-Port Static RAM Features • Automatic power-down • True Dual-Ported memory cells that allow simultaneous access of the same memory location • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • On-chip arbitration logic • 64K x 9 organization (CY7C018) • Semaphores included to permit software handshaking between ports • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power • INT flags for port-to-port communication • High-speed access: 12[1]/15/20 ns • Dual Chip Enables • Low operating power • Pin select for Master or Slave — Active: ICC = 180 mA (typical) • Commercial and Industrial temperature ranges — Standby: ISB3 = 0.05 mA (typical) • Fully asynchronous operation • Available in 100-pin TQFP; Pb-Free packages available Logic Block Diagram R/WL R/WR CE0L CE1L CEL CE0R CE1R CER OEL OER [2] 8/9 8/9 I/O0L–I/O7/8L I/O Control [3] A0L–A15/16L [3] 16/17 Address Decode I/O Control Address Decode True Dual-Ported RAM Array 16/17 16/17 [3] A0R–A15/16R 16/17 A0L–A15/16L CEL OEL R/WL SEML BUSYL INTL [2] I/O0R–I/O7/8R [3] A0R–A15/16R CER OER R/WR SEMR Interrupt Semaphore Arbitration [4] [4] BUSYR INTR M/S Notes: 1. 2. 3. 4. See page 6 for Load Conditions. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. A0–A15 for 64K devices; A0–A16 for 128K. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06041 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 6, 2005
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