CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09079V/89V/99V
CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
Features
■
High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)
True Dual-Ported memory cells which enable simultaneous
access of the same memory location
■
3.3V low operating power
■
Active= 115 mA (typical)
■
6 Flow-Through and Pipelined devices
■
Standby= 10 μA (typical)
■
32K x 8/9 organizations (CY7C09079V/179V)
■
Fully synchronous interface for easier operation
■
64K x 8/9 organizations (CY7C09089V/189V)
■
Burst counters increment addresses internally
■
128K x 8/9 organizations (CY7C09099V/199V)
■
Shorten cycle times
■
3 Modes
■
Minimize bus noise
■
Flow-Through
■
Supported in Flow-Through and Pipelined modes
■
Pipelined
■
Burst
Pipelined output mode on both ports enables fast 100 MHz
operation
0.35-micron CMOS for optimum speed and power
■
Dual Chip Enables for easy depth expansion
Automatic power down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Pb-free packages available
■
■
■
■
■
■
■
Logic Block Diagram
R/WL
R/WR
OEL
OER
CE0L
CE1L
1
0
0
0/1
1
0/1
FT/PipeL
[3]
A0–A14/15/16L
CLKL
ADSL
CNTENL
CNTRSTL
0/1
0
0
1
0/1
8/9
[2]
I/O0L–I/O7/8L
CE0R
CE1R
1
FT/PipeR
8/9
I/O
Control
[2]
I/O0R–I/O7/8R
I/O
Control
15/16/17
15/16/17
Counter/
Address
Register
Decode
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
[3]
A0–A14/15/16R
CLKR
ADSR
CNTENR
CNTRSTR
Notes
1. See page 6 for Load Conditions.
2. I/O0–I/O7 for x8 devices, I/O0–I/O8 for x9 devices.
3. A0–A14 for 32K, A0–A15 for 64K, and A0–A16 for 128K devices.
Cypress Semiconductor Corporation
Document #: 38-06043 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 10, 2008
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