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CY7C1021V30L15

製品説明
仕様・特性

0 CY7C1021V30 64K x 16 Static RAM Features • 3.0V operation (2.7V–3.3V) • High speed — tAA = 15 ns • CMOS for optimum speed/power • Low active power (L version) — 462 mW (max.) • Low CMOS Standby Power (L version) — 1.65 mW (max.) • Automatic power-down when deselected • Independent control of Upper and Lower bits • Available in a 48-ball Mini BGA package Functional Description The CY7C1021V30 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O 8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O 1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021V30 is available in a 48-ball Mini BGA package. Logic Block Diagram Pin Configuration DATA IN DRIVERS Mini BGA Top View 4 5 6 A3 A7 A6 NC A I/O1 BHE A2 A1 CE I/O 16 B I/O2 I/O3 A0 A4 I/O I/O 14 15 C VSS I/O4 NC A5 I/O V 13 CC D VCC I/O5 2 NC NC I/O VSS 12 E A9 A8 I/O I/O 11 10 F BLE OE SENSE AMPS 64K x 16 RAM Array 512 X 2048 3 I/O6 I/O7 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 1 I/O1–I/O8 I/O9–I/O16 I/O8 A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE NC A11 A10 WE I/O9 G NC COLUMN DECODER A12 A13 A14 A15 NC H 1021V30-2 1021V30-1 2CY7C1021V30 Selection Guide 7C1021V30-15 Maximum Access Time (ns) 15 Maximum Operating Current (mA) Industrial Maximum CMOS Standby Current (mA) 190 Industrial L 140 5 0.500[1] L Note: 1. In addition: ISB2 < 300 µA at 2.7V. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 1, 1999

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