041BV33
CY7C1041BV33
256K x 16 Static RAM
Features
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
• High speed
— tAA = 12 ns
• Low active power
— 612 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (600 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
Functional Description
The CY7C1041BV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
I/O0 – I/O7
I/O8 – I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Selection Guide
-12
-15
-17
-20
-25
Maximum Access Time (ns)
12
15
17
20
25
Maximum Operating Current (mA) Comm’l
190
170
160
150
130
Ind’l
-
190
180
170
150
Com’l/Ind’l
8
8
8
8
8
0.5
0.5
0.5
0.5
0.5
Maximum CMOS Standby
Current (mA)
Com’l
Cypress Semiconductor Corporation
Document #: 38-05168 Rev. **
L
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised November 15, 2001
