009
CY7C109
CY7C1009
128K x 8 Static RAM
Features
• High speed
— tAA = 10 ns
• Low active power
— 1017 mW (max., 12 ns)
• Low CMOS standby power
— 55 mW (max.), 4 mW (Low power version)
• 2.0V Data Retention (Low power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
active HIGH chip enable (CE2), an active LOW output enable
(OE), and three-state drivers. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE)
inputs LOW and chip enable two (CE2) input HIGH. Data on
the eight I/O pins (I/O0 through I/O7) is then written into the
location specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE2) HIGH. Under
these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
Functional Description
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109 / CY7C1009 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW chip enable (CE1), an
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
512 x 256 x 8
ARRAY
I/O3
I/O4
I/O5
COLUMN
DECODER
CE1
CE2
WE
I/O7
A9
A 10
A 11
A 12
A 13
A14
A15
A16
OE
I/O6
POWER
DOWN
109–1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
109–2
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
109–3
Selection Guide
7C109-10
7C1009-10
10
195
10
2
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
7C109-12
7C1009-12
12
185
10
2
7C109-15
7C1009-15
15
155
10
2
7C109-20
7C1009-20
20
140
10
—
7C109-25
7C1009-25
25
135
10
—
7C109-35
7C1009-35
35
125
10
—
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
Document #: 38-05032 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
