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CY7C144AV-25AI
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/ Slave chip select when using more than one device • 4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV) • On-chip arbitration logic • 4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV) • Semaphores included to permit software handshaking between ports • 0.35-micron CMOS for optimum speed/power • INT flag for port-to-port communication • High-speed access: 20/25 ns • Pin select for Master or Slave • Low operating power • Commercial and Industrial Temperature Ranges — Active: ICC = 115 mA (typical) — Standby: ISB3 = 10 µA (typical) • Available in 68-pin PLCC (all) and 64-pin TQFP (7C006AV & 7C144AV) • Pb-Free packages available • Fully asynchronous operation Logic Block Diagram R/WL R/WR CEL CER OEL OER [1] 8/9 8/9 I/O0L–I/O7/8L [2] A0L–A11–14L [2] I/O Control 12–15 Address Decode I/O Control Address Decode True Dual-Ported RAM Array 12–15 12–15 [2] A0R–A11–14R 12–15 A0L–A11–14L CEL OEL R/WL SEML BUSYL INTL [1] I/O0R–I/O7/8R [2] A0R–A11–14R CER OER R/WR SEMR Interrupt Semaphore Arbitration [3] [3] BUSYR INTR M/S For the most recent information, visit the Cypress web site at www.cypress.com Notes: 1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices; 3. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document #: 38-06051 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 6, 2005
CYPRESS
Cypress Semiconductor
U.S.A
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