CY7C144, CY7C145
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
Functional Description
■
True Dual-Ported Memory Cells that Enable Simultaneous
Reads of the same Memory Location
■
8K x 8 Organization (CY7C144)
■
8K x 9 Organization (CY7C145)
■
0.65-Micron CMOS for optimum Speed and Power
■
High Speed Access: 15 ns
■
Low Operating Power: ICC = 160 mA (max.)
■
Fully Asynchronous Operation
■
Automatic Power Down
■
TTL Compatible
■
Master/Slave Select Pin enables Bus Width Expansion to 16/18
Bits or more
■
Busy Arbitration Scheme provided
■
Semaphores included to permit Software Handshaking
between Ports
■
INT Flag for Port-to-Port Communication
■
Available in 68-pin PLCC, 64-pin and 80-pin TQFP
■
Pb-free Packages available
Logic Block Diagram
The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and
8K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C144/5 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5 can
be used as a standalone 64/72-Kbit dual-port static RAM or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S pin
is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or
additional discrete logic. Application areas include interprocessor/multiprocessor
designs,
communications
status
buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags, BUSY
and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
between ports or systems by means of a mail box. The
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
R/W L
R/W R
CE L
OE L
CE R
OE R
(7C145) I/O8L
I/O7L
I/O
CONTROL
I/O0L
I/O 8R(7C145)
I/O 7R
I/O
CONTROL
I/O 0R
[1, 2]
BUSYL
BUSY R [1, 2]
A 12L
A 12R
ADDRESS
DECODER
A 0L
CEL
OEL
MEMORY
ARRAY
ADDRESS
DECODER
INTERRUPT
SEMAPHORE
ARBITRATION
R/W L
A 0R
CE R
OE R
R/W R
SEM L
INT L [2]
SEMR
INTR [2]
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
Document #: 38-06034 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 26, 2009
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