69A
CY7C168A
4Kx4 RAM
Features
Functional Description
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
— tAA = 15 ns
• Low active power
— 633 mW
• Low standby power
— 110 mW
• TTL-compatible inputs and outputs
• VIH of 2.2V
• Capable of withstanding greater than 2001V electrostatic discharge
The CY7C168A is a high-performance CMOS static RAM organized as 4096 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C168A has an automatic power-down feature,
reducing the power consumption by 77% when deselected.
Writing to the device is accomplished when the Chip Select
(CE) and Write Enable (WE) inputs are both LOW. Data on the
four data input/output pins (I/O0 through I/O3) is written into the
memory location specified on the address pins (A0 through
A11).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the location specified on the
address pins will appear on the four data input/output pins
(I/O0 through I/O3).
The input/output pins remain in a high-impedance state when
Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
A4
A5
A6
A7
A8
A9
A10
A11
INPUTBUFFER
SENSE AMP
I/O0
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
128 x 128
ARRAY
1
19
3
18
4
17
5
6
7C168A 16
\
15
7
14
8
13
9
12
10
CE
GND
I/O1
20
2
11
VCC
A3
A2
A1
A0
I/O 0
I/O 1
I/O 2
I/O 3
WE
C168A-2
I/O2
I/O3
COLUMN
DECODER
CE
POWER
DOWN
(7C168A)
WE
A7 A8 A9 A10 A11
C168A-1
Selection Guide
7C168A-15
7C168A-20
7C168A-25
7C168A-35
7C168A-45
Maximum Access Time (ns)
15
20
25
35
45
Maximum Operating
Current (mA)
115
90
90
90
90
-
100
100
100
100
Commercial
Military
Cypress Semiconductor Corporation
Document #: 38-05029 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
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