182
CY7C182
8Kx9 Static RAM
Features
The CY7C182, which is oriented toward cache memory applications, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active-LOW Output Enable (OE), and threestate drivers.
• High speed
— tAA = 25 ns
• x9 organization is ideal for cache memory applications
• CMOS for optimum speed/power
• Low active power
— 770 mW
• Low standby power
— 195 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Easy memory expansion with CE1, CE2, OE options
An active-LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW, data on the nine data input/output pins
(I/O0 through I/O8) is written into the memory location addressed by the address present on the address pins (A0
through A12). Reading the device is accomplished by selecting
the device and enabling the outputs, (CE1 and OE active LOW
and CE2 active HIGH), while (WE) remains inactive or HIGH.
Under these conditions, the contents of the location addressed
by the information on address pins is present on the nine data
input/output pins.
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bits and it is manufactured using Cypress’s highperformance CMOS technology. Access times as fast as 25 ns
are available with maximum power consumption of only 770
mW.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
DIP/SOJ
Top View
A4
256 x 32 x 9
ARRAY
V CC
2
27
WE
A6
3
26
CE 2
I/O1
A7
4
25
A3
A8
5
24
A2
A9
6
23
A1
A 10
7
22
OE
A 11
8
21
A0
A 12
9
20
CE 1
I/O 0
10
19
I/O 8
I/O 1
11
18
I/O 7
I/O 2
12
17
I/O 6
I/O 3
13
16
I/O 5
GND
14
15
I/O 4
I/O2
SENSE AMPS
ROW DECODER
A1
A2
A3
A4
A5
A6
A7
A8
28
I/O0
INPUT BUFFER
1
A5
I/O3
I/O4
I/O5
I/O6
CE1
CE2
WE
POWER
DOWN
COLUMN
DECODER
I/O8
A12
A11
A10
OE
A0
A9
C182–2
I/O7
C182–1
Selection Guide
7C182-25
7C182-35
7C182-45
Maximum Access Time (ns)
25
35
45
Maximum Operating Current (mA)
140
140
140
Maximum Standby Current (mA)
35
35
35
Cypress Semiconductor Corporation
Document #: 38-05031 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
